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authorAlexey Brodkin <Alexey.Brodkin@synopsys.com>2015-12-14 17:14:46 +0300
committerAlexey Brodkin <abrodkin@synopsys.com>2016-02-20 11:19:53 +0300
commit379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1 (patch)
treedee63afdf0dd287b0daef4b3552513babff0fea3 /configs/tb100_defconfig
parent86a0df732853d1a11eb3eaa3cda688d9ef7b34e5 (diff)
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arc: cache - accommodate different L1 cache line lengths
ARC core could be configured with different L1 and L2 (AKA SLC) cache line lengths. At least these values are possible and were really used: 32, 64 or 128 bytes. Current implementation requires cache line to be selected upon U-Boot configuration and then it will only work on matching hardware. Indeed this is quite efficient because cache line length gets hardcoded during code compilation. But OTOH it makes binary less portable. With this commit we allow U-Boot to determine real L1 cache line length early in runtime and use this value later on. This extends portability of U-Boot binary a lot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'configs/tb100_defconfig')
-rw-r--r--configs/tb100_defconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig
index 27ea43f..053b74c 100644
--- a/configs/tb100_defconfig
+++ b/configs/tb100_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARC=y
-CONFIG_ARC_CACHE_LINE_SHIFT=5
CONFIG_TARGET_TB100=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_CLK_FREQ=500000000