From 379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 14 Dec 2015 17:14:46 +0300 Subject: arc: cache - accommodate different L1 cache line lengths ARC core could be configured with different L1 and L2 (AKA SLC) cache line lengths. At least these values are possible and were really used: 32, 64 or 128 bytes. Current implementation requires cache line to be selected upon U-Boot configuration and then it will only work on matching hardware. Indeed this is quite efficient because cache line length gets hardcoded during code compilation. But OTOH it makes binary less portable. With this commit we allow U-Boot to determine real L1 cache line length early in runtime and use this value later on. This extends portability of U-Boot binary a lot. Signed-off-by: Alexey Brodkin --- configs/tb100_defconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'configs/tb100_defconfig') diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig index 27ea43f..053b74c 100644 --- a/configs/tb100_defconfig +++ b/configs/tb100_defconfig @@ -1,5 +1,4 @@ CONFIG_ARC=y -CONFIG_ARC_CACHE_LINE_SHIFT=5 CONFIG_TARGET_TB100=y CONFIG_DM_SERIAL=y CONFIG_SYS_CLK_FREQ=500000000 -- cgit v1.1