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authorVictor Gallardo <vgallardo@amcc.com>2008-09-16 06:59:13 -0700
committerStefan Roese <sr@denx.de>2008-09-16 20:16:31 +0200
commit3eec160a3a405b29ce9c06920f6427b9047dd8a8 (patch)
tree14c0a3795543b2ee4d8e5bb0c63e247de469bf37 /board
parentc0d2f87d6c450128b88e73eea715fa3654f65b6c (diff)
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ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)
Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
-rw-r--r--board/amcc/kilauea/kilauea.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index f407e19..1caa2fd 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -374,3 +374,34 @@ int post_hotkeys_pressed(void)
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
+
+#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
+/*
+ * This is for quicker auto calibration boot up once WRDTR and CLKTR
+ * values for the kilauea board were determined and are therefore known.
+ *
+ * Use these scan options for PLB bus greater than or equal 200MHz
+ * else use the defaults. These options are known to return a cycle
+ * delay of T2 or better with a 200MHz PLB bus. Scanning the
+ * full list of WDTR/CLKTR should work, but currently it does not.
+ * HW team is investigating.
+ */
+/* List of (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CLKP]) pairs to try */
+struct sdram_timing quick_scan_options[] = {
+ {0, 3}, {1, 1}, {1, 2}, {1, 3},
+ {2, 1}, {2, 2}, {2, 3}, {3, 1},
+ {3, 2}, {4, 1}, {-1, -1}
+};
+
+ulong ddr_scan_option(ulong default_val)
+{
+ PPC4xx_SYS_INFO board_cfg;
+
+ get_sys_info(&board_cfg);
+
+ if (board_cfg.freqPLB >= 200000000)
+ return (ulong)(quick_scan_options);
+ else
+ return (ulong)default_val;
+}
+#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */