summaryrefslogtreecommitdiff
path: root/board
diff options
context:
space:
mode:
authorJason Liu <r64343@freescale.com>2012-12-05 14:16:20 +0800
committerJason Liu <r64343@freescale.com>2012-12-05 20:41:08 +0800
commitc738932446765f46c050e30df9d29e5fcc988d79 (patch)
treec1ff2ec2db58807c046e3a9cec77d9246d255a65 /board
parent2ff6f45780995b06faab268f6130d68565e96ba5 (diff)
downloadu-boot-imx-jb4.1.2_1.0.0-beta.zip
u-boot-imx-jb4.1.2_1.0.0-beta.tar.gz
u-boot-imx-jb4.1.2_1.0.0-beta.tar.bz2
ENGR000234991 MX6DL/ARD: Two boards met kernel dump during boot upjb4.1.2_1.0.0-beta
The issue is caused by DDR script changed io pads to DDR differential mode but forget to do the calibration data update. This patch updated the DDR script on MX6DL ARD board based on the commit on the ddr-scripts-rel: 53121e0 Updated MX6DL and MX6DQ ARD and SabreSD scripts with new calibration values for IO pads set to differential mode; Signed-off-by: Jason Liu <r64343@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mx6q_sabreauto/flash_header.S16
1 files changed, 8 insertions, 8 deletions
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S
index af70dbe..0a5abc6 100644
--- a/board/freescale/mx6q_sabreauto/flash_header.S
+++ b/board/freescale/mx6q_sabreauto/flash_header.S
@@ -386,14 +386,14 @@ MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x001F001F)
MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x001F001F)
# DQS gating, read delay, write delay calibration values
# based on calibration compare of 0x00ffff00
-MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42120218)
-MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x02030203)
-MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x4302031A)
-MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x027B0249)
-MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4A494C4A)
-MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x3A373345)
-MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3F36)
-MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x48334736)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x42190217)
+MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x017B017B)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x4176017B)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x015F016C)
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x4C4C4D4C)
+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x4A4D4C48)
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3F3F3F40)
+MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x3538382E)
# read data bit delay
MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)