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| author | Wolfgang Denk <wd@denx.de> | 2012-04-30 16:55:25 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-04-30 16:55:25 +0200 |
| commit | 4212657c53f9ed66fd5adc9da9a327e3739646fb (patch) | |
| tree | 04e2e1b049ffaa04e4d8e6e4233313ab2063e2f0 /board/gdsys/405ep/405ep.c | |
| parent | 5f6db68b42024b51a9a1fddd7d4371d2af82c090 (diff) | |
| parent | 0e60aa85c82863f34cb13145caa1d0c5255b977b (diff) | |
| download | u-boot-imx-4212657c53f9ed66fd5adc9da9a327e3739646fb.zip u-boot-imx-4212657c53f9ed66fd5adc9da9a327e3739646fb.tar.gz u-boot-imx-4212657c53f9ed66fd5adc9da9a327e3739646fb.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
* 'master' of git://git.denx.de/u-boot-ppc4xx:
powerpc/ppc4xx: Remove typedefs for gdsys FPGA
powerpc/ppc4xx: Fix typo in gdsys_fpga.h
powerpc/ppc4xx: Update gdsys board configurations
powerpc/ppc4xx: Support gdsys dlvision-10g hardware 1.20
powerpc/ppc4xx: Adapt gdsys 405ep boards to platform changes
powerpc/ppc4xx: Make gdsys 405ep boards reset more generic
powerpc/ppc4xx: Adjust environment size on neo
Diffstat (limited to 'board/gdsys/405ep/405ep.c')
| -rw-r--r-- | board/gdsys/405ep/405ep.c | 45 |
1 files changed, 21 insertions, 24 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 8b80533..bc9b7d0 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -28,12 +28,9 @@ #include <asm/ppc4xx-gpio.h> #include <asm/global_data.h> +#include "405ep.h" #include <gdsys_fpga.h> -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) @@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev) int board_early_init_f(void) { unsigned k; - unsigned ctr; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->fpga_state[k] = 0; @@ -73,26 +69,29 @@ int board_early_init_f(void) * -> ca. 15 us */ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ + return 0; +} - /* - * setup io-latches for reset - */ - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] = 0; /* - * wait for fpga-done + * reset FPGA */ + gd405ep_init(); + + gd405ep_set_fpga_reset(1); + + gd405ep_setup_hw(); + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; - while (!(in_le16((void *)LATCH2_BASE) - & CONFIG_SYS_FPGA_DONE(k))) { + while (!gd405ep_get_fpga_done(k)) { udelay(100000); if (ctr++ > 5) { gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; @@ -101,15 +100,13 @@ int board_early_init_f(void) } } - /* - * setup io-latches for boot (stop reset) - */ udelay(10); - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + + gd405ep_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); + struct ihs_fpga *fpga = + (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); #ifdef CONFIG_SYS_FPGA_NO_RFL_HI u16 *reflection_target = &fpga->reflection_low; #else |