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authorTerry Lv <r65388@freescale.com>2010-02-24 18:34:13 +0800
committerTerry Lv <r65388@freescale.com>2010-03-04 14:55:00 +0800
commitbd6578e46d1ba93ffe6e00147704d7d18c7e5573 (patch)
tree424b9a30a2e791ff267b2aaa27d0d52186693b8e /board/freescale/mx51_bbg
parent871825c1148b233fb562c09204700b59fcd28b67 (diff)
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ENGR00120520: Enable MMU for mx51 and mx35
MMU enable code is missed in mx51 and mx35 u-boot. So add these codes. Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale/mx51_bbg')
-rw-r--r--board/freescale/mx51_bbg/mx51_bbg.c20
1 files changed, 17 insertions, 3 deletions
diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c
index f4028dc..4446a63 100644
--- a/board/freescale/mx51_bbg/mx51_bbg.c
+++ b/board/freescale/mx51_bbg/mx51_bbg.c
@@ -115,7 +115,12 @@ u32 get_board_rev(void)
static inline void setup_soc_rev(void)
{
int reg;
+#ifdef CONFIG_ARCH_MMU
+ reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
+#else
reg = __REG(ROM_SI_REV);
+#endif
+
switch (reg) {
case 0x02:
system_rev = 0x51000 | CHIP_REV_1_1;
@@ -131,7 +136,7 @@ static inline void setup_soc_rev(void)
}
}
-static inline void set_board_rev()
+static inline void set_board_rev(void)
{
if ((__REG(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
system_rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
@@ -152,13 +157,13 @@ void board_mmu_init(void)
/*
* Set the TTB register
*/
- asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+ asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
/*
* Set the Domain Access Control Register
*/
i = ARM_ACCESS_DACR_DEFAULT;
- asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+ asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
/*
* First clear all TT entries - ie Set them to Faulting
@@ -197,6 +202,15 @@ void board_mmu_init(void)
X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+
+ /* Workaround for arm errata #709718 */
+ /* Setup PRRR so device is always mapped to non-shared */
+ asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
+ i &= (~(3 << 0x10));
+ asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
+
+ /* Enable MMU */
+ MMU_ON();
}
#endif