ENGR00120520: Enable MMU for mx51 and mx35

MMU enable code is missed in mx51 and mx35 u-boot.
So add these codes.

Signed-off-by: Terry Lv <r65388@freescale.com>

4 files changed, 41 insertions, 8 deletions

diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S
index e984306..64a20bd 100644
--- a/board/freescale/mx35_3stack/lowlevel_init.S
+++ b/board/freescale/mx35_3stack/lowlevel_init.S
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  *
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -300,6 +300,8 @@ lowlevel_init:
 #ifdef BRANCH_PREDICTION_ENABLE
 	mcr 15, 0, r0, c15, c2, 4
 #endif
+	mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
+	mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
 	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
 
 	/* initializes very early AIPS, what for?
diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c
index 5889a31..6480c16 100644
--- a/board/freescale/mx35_3stack/mx35_3stack.c
+++ b/board/freescale/mx35_3stack/mx35_3stack.c
@@ -75,7 +75,7 @@ int is_soc_rev(int rev)
 #ifdef CONFIG_ARCH_MMU
 void board_mmu_init(void)
 {
-	unsigned long ttb_base = PHYS_SDRAM_1 + 0x40000;
+	unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
 	unsigned long i;
 
 	/*
@@ -131,6 +131,9 @@ void board_mmu_init(void)
 	X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0,
 			  ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 			  ARM_ACCESS_PERM_RW_RW);
+
+	/* Enable MMU */
+	MMU_ON();
 }
 #endif
 
diff --git a/board/freescale/mx51_3stack/mx51_3stack.c b/board/freescale/mx51_3stack/mx51_3stack.c
index af5d3df..7ec3b1d 100644
--- a/board/freescale/mx51_3stack/mx51_3stack.c
+++ b/board/freescale/mx51_3stack/mx51_3stack.c
@@ -112,7 +112,12 @@ u32 get_board_rev(void)
 static inline void setup_soc_rev(void)
 {
 	int reg;
-	reg = __REG(ROM_SI_REV);
+#ifdef CONFIG_ARCH_MMU
+	reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
+#else
+	reg = __REG(ROM_SI_REV); /* Virtual address */
+#endif
+
 	switch (reg) {
 	case 0x02:
 		system_rev = 0x51000 | CHIP_REV_1_1;
@@ -144,13 +149,13 @@ void board_mmu_init(void)
 	/*
 	* Set the TTB register
 	*/
-	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
 
 	/*
 	* Set the Domain Access Control Register
 	*/
 	i = ARM_ACCESS_DACR_DEFAULT;
-	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+	asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
 
 	/*
 	* First clear all TT entries - ie Set them to Faulting
@@ -192,6 +197,15 @@ void board_mmu_init(void)
 	X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
 			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 			ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+
+	/* Workaround for arm errata #709718 */
+	/* Setup PRRR so device is always mapped to non-shared */
+	asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
+	i &= (~(3 << 0x10));
+	asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
+
+	/* Enable MMU */
+	MMU_ON();
 }
 #endif
 
diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c
index f4028dc..4446a63 100644
--- a/board/freescale/mx51_bbg/mx51_bbg.c
+++ b/board/freescale/mx51_bbg/mx51_bbg.c
@@ -115,7 +115,12 @@ u32 get_board_rev(void)
 static inline void setup_soc_rev(void)
 {
 	int reg;
+#ifdef CONFIG_ARCH_MMU
+	reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */
+#else
 	reg = __REG(ROM_SI_REV);
+#endif
+
 	switch (reg) {
 	case 0x02:
 		system_rev = 0x51000 | CHIP_REV_1_1;
@@ -131,7 +136,7 @@ static inline void setup_soc_rev(void)
 	}
 }
 
-static inline void set_board_rev()
+static inline void set_board_rev(void)
 {
 	if ((__REG(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
 		system_rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
@@ -152,13 +157,13 @@ void board_mmu_init(void)
 	/*
 	* Set the TTB register
 	*/
-	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/);
 
 	/*
 	* Set the Domain Access Control Register
 	*/
 	i = ARM_ACCESS_DACR_DEFAULT;
-	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+	asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/);
 
 	/*
 	* First clear all TT entries - ie Set them to Faulting
@@ -197,6 +202,15 @@ void board_mmu_init(void)
 	X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
 			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
 			ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+
+	/* Workaround for arm errata #709718 */
+	/* Setup PRRR so device is always mapped to non-shared */
+	asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
+	i &= (~(3 << 0x10));
+	asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
+
+	/* Enable MMU */
+	MMU_ON();
 }
 #endif