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| author | Terry Lv <r65388@freescale.com> | 2010-02-24 18:34:13 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2010-03-04 14:55:00 +0800 |
| commit | bd6578e46d1ba93ffe6e00147704d7d18c7e5573 (patch) | |
| tree | 424b9a30a2e791ff267b2aaa27d0d52186693b8e /board/freescale/mx35_3stack | |
| parent | 871825c1148b233fb562c09204700b59fcd28b67 (diff) | |
| download | u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.zip u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.tar.gz u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.tar.bz2 | |
ENGR00120520: Enable MMU for mx51 and mx35
MMU enable code is missed in mx51 and mx35 u-boot.
So add these codes.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale/mx35_3stack')
| -rw-r--r-- | board/freescale/mx35_3stack/lowlevel_init.S | 4 | ||||
| -rw-r--r-- | board/freescale/mx35_3stack/mx35_3stack.c | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S index e984306..64a20bd 100644 --- a/board/freescale/mx35_3stack/lowlevel_init.S +++ b/board/freescale/mx35_3stack/lowlevel_init.S @@ -1,7 +1,7 @@ /* * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> * - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -300,6 +300,8 @@ lowlevel_init: #ifdef BRANCH_PREDICTION_ENABLE mcr 15, 0, r0, c15, c2, 4 #endif + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ /* initializes very early AIPS, what for? diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c index 5889a31..6480c16 100644 --- a/board/freescale/mx35_3stack/mx35_3stack.c +++ b/board/freescale/mx35_3stack/mx35_3stack.c @@ -75,7 +75,7 @@ int is_soc_rev(int rev) #ifdef CONFIG_ARCH_MMU void board_mmu_init(void) { - unsigned long ttb_base = PHYS_SDRAM_1 + 0x40000; + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; unsigned long i; /* @@ -131,6 +131,9 @@ void board_mmu_init(void) X_ARM_MMU_SECTION(0xB20, 0xB20, 0x1E0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); + + /* Enable MMU */ + MMU_ON(); } #endif |