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authorErik van Luijk <evanluijk@interact.nl>2015-08-13 15:43:18 +0200
committerAndreas Bießmann <andreas.devel@googlemail.com>2015-08-21 15:47:02 +0200
commit0c01c3e876c0db59b4075a4a7550020f0ea25981 (patch)
tree2cfb8af2d6351192ee05826fd1b98870a0f0a023 /board/atmel/sama5d3_xplained
parent8d77576371381ade83de475bb639949b44941e8c (diff)
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arm: at91: mpddr: allow multiple DDR controllers
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller. This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [remove 'new blank line at EOF'] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'board/atmel/sama5d3_xplained')
-rw-r--r--board/atmel/sama5d3_xplained/sama5d3_xplained.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 92ed4e8..0793e4a 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -194,7 +194,7 @@ void mem_init(void)
writel(0x4, &pmc->scer);
/* DDRAM2 Controller initialize */
- ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+ ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
}
void at91_pmc_init(void)