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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-06-03 14:43:26 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-06-12 12:43:06 -0400 |
| commit | a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1 (patch) | |
| tree | 47601372443e14ab2e2ca2f4bf4ad3878121a63c /arch/arm/dts/tegra20-tec.dts | |
| parent | c7400e4882d8bf5c48f7d9ecc243987368dac2ba (diff) | |
| download | u-boot-imx-a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1.zip u-boot-imx-a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1.tar.gz u-boot-imx-a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1.tar.bz2 | |
ARM: DRA7: Update DDR IO configuration
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/dts/tegra20-tec.dts')
0 files changed, 0 insertions, 0 deletions