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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2015-06-03 14:43:26 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-06-12 12:43:06 -0400 |
| commit | a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1 (patch) | |
| tree | 47601372443e14ab2e2ca2f4bf4ad3878121a63c | |
| parent | c7400e4882d8bf5c48f7d9ecc243987368dac2ba (diff) | |
| download | u-boot-imx-a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1.zip u-boot-imx-a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1.tar.gz u-boot-imx-a5c5c5b500bd7cee5f5d260c538429fe1bcc0ae1.tar.bz2 | |
ARM: DRA7: Update DDR IO configuration
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 8d6b59e..03c2b97 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -75,16 +75,20 @@ static void io_settings_ddr3(void) writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); - writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); + + if (!is_dra7xx()) { + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); + } /* omap5432 does not use lpddr2 */ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); - writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif1_sdram_config_ext); - writel(ioregs->ctrl_emif_sdram_config_ext, - (*ctrl)->control_emif2_sdram_config_ext); + if (!is_dra72x()) + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif2_sdram_config_ext); if (is_omap54xx()) { /* Disable DLL select */ |