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| author | Tom Rini <trini@ti.com> | 2014-11-05 12:48:09 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-11-05 12:48:09 -0500 |
| commit | 625509ab0edbb7d943ad9028de3c21ca48aa58be (patch) | |
| tree | 2ea6bda524b3ad7e964f4357428de2890ad81cf4 /arch/arm/cpu | |
| parent | d5325eff10922acb11c39efece6d5f24de5b1998 (diff) | |
| parent | 0b23780ff02bdbec46fac1fe4151e2ebf1eae881 (diff) | |
| download | u-boot-imx-625509ab0edbb7d943ad9028de3c21ca48aa58be.zip u-boot-imx-625509ab0edbb7d943ad9028de3c21ca48aa58be.tar.gz u-boot-imx-625509ab0edbb7d943ad9028de3c21ca48aa58be.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 17 |
2 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index d200531..6c9c78c 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -312,6 +312,10 @@ static u32 get_ipg_per_clk(void) u32 reg, perclk_podf; reg = __raw_readl(&imx_ccm->cscmr1); +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX)) + if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) + return MXC_HCLK; /* OSC 24Mhz */ +#endif perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK; return get_ipg_clk() / (perclk_podf + 1); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dd5aaa2..affbf7f 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -240,6 +240,18 @@ static void clear_mmdc_ch_mask(void) writel(0, &mxc_ccm->ccdr); } +#ifdef CONFIG_MX6SL +static void set_preclk_from_osc(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = readl(&mxc_ccm->cscmr1); + reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; + writel(reg, &mxc_ccm->cscmr1); +} +#endif + int arch_cpu_init(void) { init_aips(); @@ -255,6 +267,11 @@ int arch_cpu_init(void) if (mxc_get_clock(MXC_ARM_CLK) == 396000000) set_ahb_rate(132000000); + /* Set perclk to source from OSC 24MHz */ +#if defined(CONFIG_MX6SL) + set_preclk_from_osc(); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifdef CONFIG_APBH_DMA |