Merge branch 'master' of git://git.denx.de/u-boot-arm

15 files changed, 257 insertions, 41 deletions

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..ee8c2b3 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS	+= cache_v7.o
 COBJS	+= cpu.o
 COBJS	+= syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
 SOBJS	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 2b584e0..1c8b617 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -55,6 +55,9 @@ void spl_board_init(void)
 #ifdef CONFIG_SPL_NAND_SUPPORT
 	gpmc_init();
 #endif
+#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
+	arch_misc_init();
+#endif
 }
 
 int board_mmc_init(bd_t *bis)
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
index 9f8bc93..36bea5f 100644
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -56,8 +56,9 @@ int timer_init(void)
 		&timer_base->tclr);
 
 	/* reset time, capture current incrementer value time */
-	gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-	gd->tbl = 0;		/* start "advancing" time stamp from 0 */
+	gd->arch.lastinc = readl(&timer_base->tcrr) /
+					(TIMER_CLOCK / CONFIG_SYS_HZ);
+	gd->arch.tbl = 0;	/* start "advancing" time stamp from 0 */
 
 	return 0;
 }
@@ -91,14 +92,15 @@ ulong get_timer_masked(void)
 	/* current tick value */
 	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
+	if (now >= gd->arch.lastinc) {	/* normal mode (non roll) */
 		/* move stamp fordward with absoulte diff ticks */
-		gd->tbl += (now - gd->lastinc);
-	else	/* we have rollover of incrementer */
-		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
-			     - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {	/* we have rollover of incrementer */
+		gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+				CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c
index bb0e795..e78c716 100644
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ b/arch/arm/cpu/armv7/s5p-common/timer.c
@@ -105,8 +105,8 @@ void reset_timer_masked(void)
 	struct s5p_timer *const timer = s5p_get_base_timer();
 
 	/* reset time */
-	gd->lastinc = readl(&timer->tcnto4);
-	gd->tbl = 0;
+	gd->arch.lastinc = readl(&timer->tcnto4);
+	gd->arch.tbl = 0;
 }
 
 unsigned long get_timer_masked(void)
@@ -123,14 +123,14 @@ unsigned long get_current_tick(void)
 	unsigned long now = readl(&timer->tcnto4);
 	unsigned long count_value = readl(&timer->tcntb4);
 
-	if (gd->lastinc >= now)
-		gd->tbl += gd->lastinc - now;
+	if (gd->arch.lastinc >= now)
+		gd->arch.tbl += gd->arch.lastinc - now;
 	else
-		gd->tbl += gd->lastinc + count_value - now;
+		gd->arch.tbl += gd->arch.lastinc + count_value - now;
 
-	gd->lastinc = now;
+	gd->arch.lastinc = now;
 
-	return gd->tbl;
+	return gd->arch.tbl;
 }
 
 /*
diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c
index 321e9b4..efa28c2 100644
--- a/arch/arm/cpu/armv7/socfpga/timer.c
+++ b/arch/arm/cpu/armv7/socfpga/timer.c
@@ -80,16 +80,16 @@ ulong get_timer_masked(void)
 {
 	/* current tick value */
 	ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
-	if (gd->lastinc >= now) {
+	if (gd->arch.lastinc >= now) {
 		/* normal mode (non roll) */
 		/* move stamp forward with absolute diff ticks */
-		gd->tbl += gd->lastinc - now;
+		gd->arch.tbl += gd->arch.lastinc - now;
 	} else {
 		/* we have overflow of the count down timer */
-		gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+		gd->arch.tbl += TIMER_LOAD_VAL - gd->arch.lastinc + now;
 	}
-	gd->lastinc = now;
-	return gd->tbl;
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /*
@@ -98,7 +98,8 @@ ulong get_timer_masked(void)
 void reset_timer(void)
 {
 	/* capture current decrementer value time */
-	gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+	gd->arch.lastinc = read_timer() /
+				(CONFIG_TIMER_CLOCK_KHZ / CONFIG_SYS_HZ);
 	/* start "advancing" time stamp from 0 */
-	gd->tbl = 0;
+	gd->arch.tbl = 0;
 }
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index dcc1f83..6b59529d 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -251,12 +251,12 @@ ENTRY(c_runtime_cpu_setup)
 /*
  * Move vector table
  */
-#if !defined(CONFIG_TEGRA20)
+#if !defined(CONFIG_TEGRA)
 	/* Set vector address in CP15 VBAR register */
 	ldr     r0, =_start
 	add     r0, r0, r9
 	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
-#endif /* !Tegra20 */
+#endif /* !Tegra */
 
 	bx	lr
 
diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile
new file mode 100644
index 0000000..eb98c8e
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra114/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra114/config.mk b/arch/arm/cpu/armv7/tegra114/config.mk
new file mode 100644
index 0000000..cb1a19d
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra114/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+CONFIG_ARCH_DEVICE_TREE := tegra114
diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile
new file mode 100644
index 0000000..04adb52
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra30/config.mk b/arch/arm/cpu/armv7/tegra30/config.mk
new file mode 100644
index 0000000..719ca81
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra30/config.mk
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+CONFIG_ARCH_DEVICE_TREE := tegra30
diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c
index 79aad99..a4b88f3 100644
--- a/arch/arm/cpu/armv7/u8500/timer.c
+++ b/arch/arm/cpu/armv7/u8500/timer.c
@@ -100,12 +100,14 @@ ulong get_timer_masked(void)
 	/* current tick value */
 	ulong now = TICKS_TO_HZ(READ_TIMER());
 
-	if (now >= gd->lastinc)	/* normal (non rollover) */
-		gd->tbl += (now - gd->lastinc);
-	else			/* rollover */
-		gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
+	if (now >= gd->arch.lastinc) {	/* normal (non rollover) */
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	} else {			/* rollover */
+		gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
+					gd->arch.lastinc) + now;
+	}
+	gd->arch.lastinc = now;
+	return gd->arch.tbl;
 }
 
 /* Delay x useconds */
@@ -132,7 +134,7 @@ ulong get_timer(ulong base)
 /*
  * Emulation of Power architecture long long timebase.
  *
- * TODO: Support gd->tbu for real long long timebase.
+ * TODO: Support gd->arch.tbu for real long long timebase.
  */
 unsigned long long get_ticks(void)
 {
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile
index 499ace4..388085d 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/cpu/armv7/zynq/Makefile
@@ -30,6 +30,7 @@ LIB	= $(obj)lib$(SOC).o
 
 COBJS-y	:= timer.o
 COBJS-y	+= cpu.o
+COBJS-y	+= slcr.o
 
 COBJS	:= $(COBJS-y)
 
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index ab615cc..e8f4c19 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -21,11 +21,37 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
 
-inline void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+	zynq_slcr_unlock();
+	/* remap DDR to zero, FILTERSTART */
+	writel(0, &scu_base->filter_start);
+
+	/* Device config APB, unlock the PCAP */
+	writel(0x757BDF0D, &devcfg_base->unlock);
+	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+	/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+	writel(0x1F, &slcr_base->ocm_cfg);
+	/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+	writel(0x0, &slcr_base->fpga_rst_ctrl);
+	/* TZ_DDR_RAM, Set DDR trust zone non-secure */
+	writel(0xFFFFFFFF, &slcr_base->trust_zone);
+	/* Set urgent bits with register */
+	writel(0x0, &slcr_base->ddr_urgent_sel);
+	/* Urgent write, ports S2/S3 */
+	writel(0xC, &slcr_base->ddr_urgent);
+
+	zynq_slcr_lock();
+}
 
 void reset_cpu(ulong addr)
 {
+	zynq_slcr_cpu_reset();
 	while (1)
 		;
 }
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
new file mode 100644
index 0000000..788a8fd
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+
+#define SLCR_LOCK_MAGIC		0x767B
+#define SLCR_UNLOCK_MAGIC	0xDF0D
+
+static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
+
+void zynq_slcr_lock(void)
+{
+	if (!slcr_lock)
+		writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+}
+
+void zynq_slcr_unlock(void)
+{
+	if (slcr_lock)
+		writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+}
+
+/* Reset the entire system */
+void zynq_slcr_cpu_reset(void)
+{
+	/*
+	 * Unlock the SLCR then reset the system.
+	 * Note that this seems to require raw i/o
+	 * functions or there's a lockup?
+	 */
+	zynq_slcr_unlock();
+
+	/*
+	 * Clear 0x0F000000 bits of reboot status register to workaround
+	 * the FSBL not loading the bitstream after soft-reboot
+	 * This is a temporary solution until we know more.
+	 */
+	clrbits_le32(&slcr_base->reboot_status, 0xF000000);
+
+	writel(1, &slcr_base->pss_rst_ctrl);
+}
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
index 323e7b5..45b405a 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -83,9 +83,9 @@ int timer_init(void)
 								emask);
 
 	/* Reset time */
-	gd->lastinc = readl(&timer_base->counter) /
+	gd->arch.lastinc = readl(&timer_base->counter) /
 					(TIMER_TICK_HZ / CONFIG_SYS_HZ);
-	gd->tbl = 0;
+	gd->arch.tbl = 0;
 
 	return 0;
 }
@@ -100,16 +100,16 @@ ulong get_timer_masked(void)
 
 	now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
 
-	if (gd->lastinc >= now) {
+	if (gd->arch.lastinc >= now) {
 		/* Normal mode */
-		gd->tbl += gd->lastinc - now;
+		gd->arch.tbl += gd->arch.lastinc - now;
 	} else {
 		/* We have an overflow ... */
-		gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+		gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
 	}
-	gd->lastinc = now;
+	gd->arch.lastinc = now;
 
-	return gd->tbl;
+	return gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)