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| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2017-02-02 15:02:00 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-02-03 14:31:45 -0800 |
| commit | add63f94a9c3bbe1af3fdf3f4c56a5185a4c0504 (patch) | |
| tree | 42764dc1d5255e15910c9df403ed2969379cdb96 /README | |
| parent | 068789773d0b369a6a64120776932f912d183f61 (diff) | |
| download | u-boot-imx-add63f94a9c3bbe1af3fdf3f4c56a5185a4c0504.zip u-boot-imx-add63f94a9c3bbe1af3fdf3f4c56a5185a4c0504.tar.gz u-boot-imx-add63f94a9c3bbe1af3fdf3f4c56a5185a4c0504.tar.bz2 | |
arch: powerpc: update the eLBC IP input clock
eLBC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock ratio register (LCRR) used in
current implementation governs eLBC IP output cloc.
Update sys_info->freq_localbus to represent eLBC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -507,6 +507,9 @@ The following options need to be configured: CONFIG_SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller). + CONFIG_SYS_FSL_LBC_CLK_DIV + Defines divider of platform clock(clock input to eLBC controller). + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details |