From add63f94a9c3bbe1af3fdf3f4c56a5185a4c0504 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 2 Feb 2017 15:02:00 +0530 Subject: arch: powerpc: update the eLBC IP input clock eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- README | 3 +++ 1 file changed, 3 insertions(+) (limited to 'README') diff --git a/README b/README index 9fda381..b27e757 100644 --- a/README +++ b/README @@ -507,6 +507,9 @@ The following options need to be configured: CONFIG_SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller). + CONFIG_SYS_FSL_LBC_CLK_DIV + Defines divider of platform clock(clock input to eLBC controller). + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details -- cgit v1.1