IGEP0046: SPL and UBOOT Testisee_imx_v2017.03_4.9.11_1.0.0_ga_TEST

it was created the following source files in board/isee/common: igep_test.c and igep_test.h
it was CLEARED igep board folders that do not belong to u-boot-imx like igep00x0 and igep0030

Signed-off-by: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>

35 files changed, 1286 insertions, 1470 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3c5209a..43943d2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1245,7 +1245,6 @@ source "board/gumstix/pepper/Kconfig"
 source "board/h2200/Kconfig"
 source "board/hisilicon/hikey/Kconfig"
 source "board/imx31_phycore/Kconfig"
-source "board/isee/igep0033/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/phytec/pcm052/Kconfig"
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index 933fcba..16e5aab 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -31,12 +31,6 @@ config TARGET_DEVKIT8000
 config TARGET_OMAP3_EVM
 	bool "TI OMAP3 EVM"
 
-config TARGET_OMAP3_IGEP00X0
-	bool "IGEP"
-	select DM
-	select DM_SERIAL
-	select DM_GPIO
-
 config TARGET_OMAP3_OVERO
 	bool "OMAP35xx Gumstix Overo"
 	select DM
@@ -105,7 +99,6 @@ source "board/compulab/cm_t35/Kconfig"
 source "board/compulab/cm_t3517/Kconfig"
 source "board/timll/devkit8000/Kconfig"
 source "board/ti/evm/Kconfig"
-source "board/isee/igep00x0/Kconfig"
 source "board/overo/Kconfig"
 source "board/logicpd/zoom1/Kconfig"
 source "board/ti/am3517crane/Kconfig"
diff --git a/board/isee/common/Makefile b/board/isee/common/Makefile
new file mode 100644
index 0000000..9606fd3
--- /dev/null
+++ b/board/isee/common/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+#
+# Source file for IGEP0046 board
+#
+# Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_SYS_I2C)		+= igep_eeprom.o
+obj-$(CONFIG_SYS_I2C)		+= igep_test.o
diff --git a/board/isee/common/igep_common.h b/board/isee/common/igep_common.h
index 17ec5dd..b67c951 100644
--- a/board/isee/common/igep_common.h
+++ b/board/isee/common/igep_common.h
@@ -13,15 +13,18 @@
 
 #define IGEP_MAGIC_ID 0x6D6A6DE4
 
+
+
+/* BOARD UUID INFO TEST STRUCT */
 struct __attribute__((packed)) igep_mf_setup  {
-    u32 magic_id;			/* eeprom magic id */
-    u32 crc32;				/* eeprom crc32 */
+    u32 magic_id;			    /* eeprom magic id */
+    u32 crc32;                  /* eeprom crc32 */
     char board_uuid [36];		/* board identifier */
     char board_pid [16];		/* product identifier */
-    char model [8];			/* board model */
-    char variant [9];		/* board version */
+    char model [8];             /* board model */
+    char variant [9];           /* board version */
     char manf_of[6];			/* manufacturer order of fabrication */
-    char manf_timestamp[19];		/* manufacturer timestamp */
+    char manf_timestamp[19];	/* manufacturer timestamp */
     uchar bmac0[17];			/* MAC 0 - default */
     uchar bmac1[17];			/* MAC 1 */
 };
diff --git a/board/isee/common/igep_eeprom.c b/board/isee/common/igep_eeprom.c
index ff2e4e2..98953bc 100644
--- a/board/isee/common/igep_eeprom.c
+++ b/board/isee/common/igep_eeprom.c
@@ -5,7 +5,7 @@
  *
  * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
  */
 
 #include <common.h>
@@ -13,7 +13,7 @@
 #include <asm/arch/sys_proto.h>
 
 
-int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size)
+int eeprom_write_setup (uint16_t s_addr, const char* data, u32 size)
 {
     u32 i;
     u32 remain = size % 32;
@@ -22,18 +22,18 @@ int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size)
         if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
             return -1;
         }
-        udelay(5000);
+        mdelay(10);
     }
     if(remain > 0){
         if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
             return -1;
         else
-            udelay(5000);
+            mdelay(10);
     }
     return 0;
 }
 
-int eeprom_read_setup (uint8_t s_addr, char* data, u32 size)
+int eeprom_read_setup (uint16_t s_addr, char* data, u32 size)
 {
     u32 i;
     u32 remain = size % 32;
@@ -53,10 +53,19 @@ int check_eeprom (void)
 {
     i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
     /* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		printf("Could not probe the EEPROM at 0x%x\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
-		return -1;
-	}
-	return 0;
+    if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+        printf("Could not probe the EEPROM at 0x%x\n",
+               CONFIG_SYS_I2C_EEPROM_ADDR);
+        return -1;
+    }
+    return 0;
 }
+
+unsigned int parse_char(char c)
+{
+    if ('0' <= c && c <= '9') return c - '0';
+    if ('a' <= c && c <= 'f') return 10 + c - 'a';
+    if ('A' <= c && c <= 'F') return 10 + c - 'A';
+    
+    return 0;
+}
\ No newline at end of file
diff --git a/board/isee/common/igep_eeprom.h b/board/isee/common/igep_eeprom.h
index db56247..f488f89 100644
--- a/board/isee/common/igep_eeprom.h
+++ b/board/isee/common/igep_eeprom.h
@@ -11,7 +11,8 @@
 #ifndef __EEPROM_BOARD_HELPER__
 #define __EEPROM_BOARD_HELPER__
 
-int eeprom_write_setup (uint8_t s_addr, const char* data, u32 size);
-int eeprom_read_setup (uint8_t s_addr, char* data, u32 size);
+int eeprom_write_setup (uint16_t s_addr, const char* data, u32 size);
+int eeprom_read_setup (uint16_t s_addr, char* data, u32 size);
 int check_eeprom (void);
+unsigned int parse_char(char c);
 #endif
diff --git a/board/isee/common/igep_test.c b/board/isee/common/igep_test.c
new file mode 100644
index 0000000..f49fcfa
--- /dev/null
+++ b/board/isee/common/igep_test.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * Source file for Test functions to help board code
+ *
+ * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/sys_proto.h>
+#include "igep_eeprom.h"
+#include "igep_common.h"
+#include "igep_test.h"
+
+int test_eeprom(void)
+{
+	u32 crc_value  = 0;
+	u32 crc_save_value = 0;
+	//u32 *ptrt;
+    /* This is the TEST STRUCT INITIALIZED WITH KNOWN VALUES, KNOWN CRC TO TEST EEPROM */
+	/* CRC was calcualted with same struct using 0 value in crc field, now set to 541599072*/
+	struct igep_mf_setup test_struct = {
+	1234567890,
+	541599072,
+	"0b9e485e-dcfc-11e8-8f39-080027541785",
+	"120311D4EA9C35AC",
+	"IGEP1234",
+	"TEST-TEST",
+	"PROMAX",
+	"2019-01-24 11:59:31",
+	"02:00:00:00:00:01",
+	"02:de:fa:00:00:77"
+	};
+	/* Auxiliar struct */
+	struct igep_mf_setup aux_config;
+
+    /* Here  we will act different from normal u-boot, first we will write TEST structure and then we will read CRC and compare it with
+	known CRC */
+	/* But first of all we need to read it and calculate it */
+    if(check_eeprom() != 0){
+		puts("EEPROM: not found\n");
+		return 1;
+    }else{
+    	/* Write IGEP TEST STRUCT */
+		if(eeprom_write_setup(EEPROM_TEST_STRUCT_OFF*32, (char*) &test_struct, sizeof(struct igep_mf_setup))){
+			puts("EEPROM: write fail\n");
+			return 1;	
+		}else{
+			/* Let's Read TEST STRUCT and put it in aux config to see how it went */
+			if(eeprom_read_setup(EEPROM_TEST_STRUCT_OFF*32, (char*) &aux_config, sizeof(struct igep_mf_setup))){
+				puts("EEPROM: read fail\n");
+				return 1;
+			}else{
+		
+	  			/* Store read crc32 */
+	   			crc_save_value = aux_config.crc32;
+	   			//printf("Original crc32: 0x%x \n", test_struct.crc32);
+	   			//printf("Readed crc32: 0x%x \n", aux_config.crc32);
+	   			aux_config.crc32 = 0;
+	  			/* Fine now let's calculate the CRC32 of readed config and print it by screen */
+	  			crc_value = crc32(0, (const unsigned char*) &aux_config, sizeof(struct igep_mf_setup));
+	  			//printf("Calculated crc32: 0x%x \n", crc_value);
+	  			/* Now lets compare both CRC, in this TEST IT SHOULD ALWAYS BE OK! OTHERWISE EEPROM TEST FAILED */
+				if(crc_save_value != crc_value){
+       				puts("EEPROM: CRC32 failed, EEPROM FAIL\n");
+       				return 1;				
+				}
+			}	
+		}
+	}
+	return 0;
+}
+
+int burn_test(char* to_burn, uint64_t count, int offset)
+{
+	struct igep_bootloaders_test aux_config;
+
+	if(check_eeprom() != 0){
+		puts("EEPROM: not found\n");
+		return 1;
+    }else{
+		if(eeprom_write_setup((offset+count)*32, to_burn, sizeof(struct igep_bootloaders_test))){
+			puts("EEPROM: write fail\n");
+			return 1;	
+		}else{
+			if(eeprom_read_setup((offset+count)*32, (char*) &aux_config, sizeof(struct igep_bootloaders_test))){
+				printf("EEPROM: read fail\n");	
+			}else{
+				printf("EEPROM: read %d bytes \n", sizeof(struct igep_bootloaders_test));
+	  			printf("---------------------------- |!| TEST STRUCT |!| ----------------------------\n");
+  				printf("Test Magic_id: 0x%x \n", aux_config.magic_id);
+  				printf("Test Result: 0x%x \n", aux_config.test);
+  				printf("CPUID: 0x%llx \n", aux_config.cpuid);
+  				printf("crc32: 0x%x \n", aux_config.crc32);
+	  			printf("-----------------------------------------------------------------------------\n");
+	  		}
+		}
+	}
+	return 0;
+}
+
+int burn_test_counter(char* to_burn, int offset)
+{
+	struct igep_bootloaders_counter aux_config;
+
+	if(check_eeprom() != 0){
+		puts("EEPROM: not found\n");
+		return 1;
+    }else{
+		if(eeprom_write_setup(offset*32, to_burn, sizeof(struct igep_bootloaders_counter))){
+			puts("EEPROM: write fail\n");
+			return 1;	
+		}else{
+			if(eeprom_read_setup(offset*32, (char*) &aux_config, sizeof(struct igep_bootloaders_counter))){
+				printf("EEPROM: read fail\n");	
+			}else{
+				printf("EEPROM: read %d bytes \n", sizeof(struct igep_bootloaders_counter));
+	  			printf("---------------------------- |!| TEST COUNTER STRUCT |!| ----------------------------\n");
+  				printf("Test Magic_id: 0x%x \n", aux_config.magic_id);
+  				printf("Number of Tests: 0x%llx \n", aux_config.count);
+  				printf("crc32: 0x%x \n", aux_config.crc32);
+	  			printf("-----------------------------------------------------------------------------\n");
+	  		}
+		}
+	}
+	return 0;
+}
+
+int test_counter_check(int offset)
+{
+	u32 crc_value  = 0;
+	u32 crc_save_value = 0;
+	struct igep_bootloaders_counter aux_config;
+	
+	if(check_eeprom() != 0){
+		puts("EEPROM: not found\n");
+		return 1;
+    }else{
+		if(eeprom_read_setup(offset*32, (char*) &aux_config, sizeof(struct igep_bootloaders_counter))){
+			printf("EEPROM: read fail\n");	
+			return 1;
+		}else{
+			printf("EEPROM: read %d bytes \n", sizeof(struct igep_bootloaders_counter));
+	  		printf("---------------------------- |!| TEST COUNTER STRUCT |!| ----------------------------\n");
+  			printf("Counter Magic_id: 0x%x \n", aux_config.magic_id);
+  			printf("Number of Tests: 0x%llx \n", aux_config.count);
+  			printf("crc32: 0x%x \n", aux_config.crc32);
+	  		printf("-----------------------------------------------------------------------------\n");
+	   		crc_save_value = aux_config.crc32;
+	   		aux_config.crc32 = 0;
+	  		crc_value = crc32(0, (const unsigned char*) &aux_config, sizeof(struct igep_bootloaders_counter));
+			if(crc_save_value != crc_value){
+       			puts("EEPROM: CRC32 failed, EEPROM FAIL\n");
+       			return 1;				
+			}
+  		}
+  	}
+	return 0;
+}
+
+uint64_t test_counter_get(int offset)
+{	
+	struct igep_bootloaders_counter aux_config;
+	check_eeprom();
+	eeprom_read_setup(offset*32, (char*) &aux_config, sizeof(struct igep_bootloaders_counter));
+	printf("EEPROM: read %d bytes \n", sizeof(struct igep_bootloaders_counter));
+	printf("---------------------------- |!| TEST COUNTER STRUCT |!| ----------------------------\n");
+  	printf("Counter magic_id: 0x%x \n", aux_config.magic_id);
+  	printf("Number of Tests: 0x%llx \n", aux_config.count);
+  	printf("crc32: 0x%x \n", aux_config.crc32);
+	printf("-----------------------------------------------------------------------------\n");
+	return aux_config.count;
+}
+
+int save_test(uint16_t test, uint32_t id, uint64_t cpuid)
+{
+	struct igep_bootloaders_test test_to_burn;
+	struct igep_bootloaders_counter test_counter_to_burn;
+	int crc_value = 0;
+	uint64_t counter = 0;
+	uint32_t starting_off = 0;
+	uint32_t counter_off = 0;
+	uint32_t counter_id = 0;
+	uint64_t offset = 0;
+
+	if (id == SPL_MAGIC_ID){
+		/* SPL CASE */
+		starting_off = SPL_START_TEST_OFF;
+		counter_off = SPL_TEST_COUNTER_OFF;
+		counter_id = SPL_MAGIC_ID_COUNTER;
+	}else {
+		/* UB CASE */
+		starting_off = UB_START_TEST_OFF;
+		counter_off = UB_TEST_COUNTER_OFF;
+		counter_id = UB_MAGIC_ID_COUNTER;
+	}
+
+	/* Prepare final struct (16 bytes) */
+	test_to_burn.magic_id = id;
+	test_to_burn.test = test;
+	test_to_burn.cpuid = cpuid;
+	test_to_burn.crc32 = 0;
+	/* Calculate crc and final set up */
+	crc_value = crc32(0, (const unsigned char*) &test_to_burn, sizeof(struct igep_bootloaders_test));
+	test_to_burn.crc32 = crc_value;
+
+	/* Erase counter if needed */
+	//erase_eeprom_counter(counter_id, counter_off);
+
+	/* Check SPL Test Counter struct integrity */
+	if (test_counter_check(counter_off)){
+		puts("COUNTER INTEGRITY FAIL.\n");
+		erase_eeprom_counter(counter_id, counter_off);
+	}
+		/* Get counter */
+		puts("COUNTER INTEGRITY OK.\n");
+		counter = test_counter_get(counter_off);
+		/* Do module to get circular offset */
+		offset = counter % UB_START_TEST_OFF;
+
+		/*if UB add natural offset
+		if (id == UB_MAGIC_ID){
+			offset = counter + UB_START_TEST_OFF;
+		}
+		*/
+
+		printf("Counter: 0x%llx\n",counter);
+		printf("Offset: 0x%llx\n",offset);
+
+		/* Burn TEST in offset addr */
+		if (burn_test((char*)&test_to_burn, offset, starting_off)){
+			puts("BURN TEST FAIL.\n");
+			return 1;
+		}else{
+			puts("BURN TEST OK.\n");
+			/* add 1 to counter and burn spl test counter */
+			counter = counter + 1;		
+			printf("Now Counter is: 0x%llx\n",counter);
+
+			test_counter_to_burn.magic_id = counter_id;
+			test_counter_to_burn.count = counter;
+			test_counter_to_burn.crc32 = 0;
+			/* Calculate crc and final set up */
+			crc_value = crc32(0, (const unsigned char*) &test_counter_to_burn, sizeof(struct igep_bootloaders_counter));
+			test_counter_to_burn.crc32 = crc_value;
+			/* Burn updated counter */
+			if (burn_test_counter((char*)&test_counter_to_burn, counter_off)){
+				puts("ISEE TEST FAIL.\n");
+				return 1;
+			}
+		}
+	return 0;
+}
+
+uint16_t load_test(uint32_t id)
+{
+	uint64_t counter = 0;
+	uint32_t counter_off = 0;
+	struct igep_bootloaders_test aux_config;
+	uint64_t offset = 0;
+
+	if (id == SPL_MAGIC_ID_COUNTER){
+		/* SPL CASE */
+		counter_off = SPL_TEST_COUNTER_OFF;
+	}else {
+		/* UB CASE */
+		counter_off = UB_TEST_COUNTER_OFF;
+	}
+
+	/* Check SPL Test Counter struct integrity */
+	if (test_counter_check(counter_off)){
+		puts("COUNTER INTEGRITY FAIL.\n");
+		return 0x4000;
+	}else{
+		
+		/* Get counter */
+		puts("COUNTER INTEGRITY OK.\n");
+		counter = test_counter_get(counter_off);
+
+		/* Do module to get circular offset */
+		offset = counter % UB_START_TEST_OFF;
+
+		if (offset!=0)
+		{
+			offset = offset - 1;
+		}
+
+		if (id == UB_MAGIC_ID_COUNTER){
+		/* Add UB natural offset */
+			offset = offset + UB_START_TEST_OFF;
+		}
+		
+		printf("Counter: 0x%llx\n",counter);
+		printf("Offset: 0x%llx\n",offset);
+
+		/* Obtain test at offset counter */
+		if(eeprom_read_setup((offset)*32, (char*) &aux_config, sizeof(struct igep_bootloaders_test))){
+			printf("EEPROM: read fail\n");
+			return 0x4000;
+		}else{
+			printf("EEPROM: read %d bytes \n", sizeof(struct igep_bootloaders_test));
+	  		printf("---------------------------- |!| TEST STRUCT |!| ----------------------------\n");
+  			printf("Test Magic_id: 0x%x \n", aux_config.magic_id);
+  			printf("Test Result: 0x%x \n", aux_config.test);
+  			printf("CPUID: 0x%llx \n", aux_config.cpuid);
+  			printf("crc32: 0x%x \n", aux_config.crc32);
+	  		printf("-----------------------------------------------------------------------------\n");
+	  		return aux_config.test;
+	  	}
+	}
+}
+
+
+
+int erase_eeprom_counter(uint32_t id, int counter_off){
+
+	int crc_value = 0;
+	struct igep_bootloaders_counter test_counter_to_burn;
+	/* This will erase counter and enable a default one of 0, uncomment it to test */
+	puts("Creating default counter struct.\n");
+	test_counter_to_burn.magic_id = id;
+	test_counter_to_burn.count = 0;
+	test_counter_to_burn.crc32 = 0;
+	crc_value = crc32(0, (const unsigned char*) &test_counter_to_burn, sizeof(struct igep_bootloaders_counter));
+	test_counter_to_burn.crc32 = crc_value;
+	burn_test_counter((char*)&test_counter_to_burn,counter_off);
+	puts("Creation OK.\n");
+	return 0;
+}
\ No newline at end of file
diff --git a/board/isee/common/igep_test.h b/board/isee/common/igep_test.h
new file mode 100644
index 0000000..30aa0a2
--- /dev/null
+++ b/board/isee/common/igep_test.h
@@ -0,0 +1,58 @@
+/* Header file for Test Functions to help header code */
+
+#ifndef __TEST_HEADER__
+#define __TEST_HEADER__
+
+/* Magics that are involved */
+#define SPL_MAGIC_ID  					0xdadd
+#define UB_MAGIC_ID 					0xbebb
+#define SPL_MAGIC_ID_COUNTER  			0xdadadada
+#define UB_MAGIC_ID_COUNTER 			0xbebabeba
+#define SPL_START_TEST_OFF				0
+#define UB_START_TEST_OFF				58
+#define EEPROM_TEST_STRUCT_OFF			116
+#define EEPROM_ISEE_BOARD_STRUCT_OFF	121
+#define SPL_TEST_COUNTER_OFF			126
+#define UB_TEST_COUNTER_OFF				127
+#define KNOWN_CRC_CUSTOM_1MB			0x1997c7c7
+
+#define KNOWN_CRC_CUSTOM_1MB_1			0x79f08ba2
+#define KNOWN_CRC_CUSTOM_1MB_2			0x177dfc20
+#define KNOWN_CRC_CUSTOM_1MB_3			0xa5be2ae0
+#define KNOWN_CRC_CUSTOM_1MB_4			0xa8ced8e3
+
+
+/* CRC PATTERNS FOR RAM TEST */
+#define CRC_PATTERN1					0x0000AAAA
+#define CRC_PATTERN2					0x00005555
+#define CRC_PATTERN3					0x0000CCCC
+#define CRC_PATTERN4					0x33330000
+#define CRC_PATTERN5					0x99990000
+#define CRC_PATTERN6					0x66660000
+
+/* Structs that are involved */
+/* SPL / UBOOT RESULT TEST STRUCT */ 
+struct __attribute__((packed)) igep_bootloaders_test  {
+    u16 magic_id;               /* SPL or uboot magic id for result of test struct*/
+    u16 test;                   /* Results of test */
+    uint64_t cpuid;             /* CPU ID */
+    u32 crc32;                  /* CRC32 of the entire struct */
+};
+
+/* SPL / UBOOT COUNTER TEST STRUCT */
+struct __attribute__((packed)) igep_bootloaders_counter  {
+    u32 magic_id;               /* SPL or uboot magic id for counter test struct */
+    uint64_t count;             /* Counter */
+    u32 crc32;                  /* CRC32 of the entire struct */
+};
+
+/* Functions that are involved */
+int test_eeprom(void);
+int burn_test(char* t, uint64_t count, int offset);
+int burn_test_counter(char* t2, int offset);
+int test_counter_check(int offset);
+uint64_t test_counter_get(int offset);
+int save_test(uint16_t test, uint32_t id, uint64_t cpuid);
+uint16_t load_test(uint32_t id);
+int erase_eeprom_counter (uint32_t id, int offset);
+#endif
diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig
deleted file mode 100644
index e989e4b..0000000
--- a/board/isee/igep0033/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_AM335X_IGEP0033
-
-config SYS_BOARD
-	default "igep0033"
-
-config SYS_VENDOR
-	default "isee"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "am335x_igep0033"
-
-endif
diff --git a/board/isee/igep0033/MAINTAINERS b/board/isee/igep0033/MAINTAINERS
deleted file mode 100644
index bd8a1f2..0000000
--- a/board/isee/igep0033/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IGEP0033 BOARD
-M:	Enric Balletbo i Serra <eballetbo@gmail.com>
-S:	Maintained
-F:	board/isee/igep0033/
-F:	include/configs/am335x_igep0033.h
-F:	configs/am335x_igep0033_defconfig
diff --git a/board/isee/igep0033/Makefile b/board/isee/igep0033/Makefile
deleted file mode 100644
index fc985b4..0000000
--- a/board/isee/igep0033/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile
-#
-# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= mux.o
-endif
-
-obj-y	+= board.o
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
deleted file mode 100644
index 5fea7ff..0000000
--- a/board/isee/igep0033/board.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Board functions for IGEP COM AQUILA based boards
- *
- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#ifdef CONFIG_SPL_BUILD
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
-	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
-	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
-	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = K4B2G1646EBIH9_RATIO,
-	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
-
-	.cmd1csratio = K4B2G1646EBIH9_RATIO,
-	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
-
-	.cmd2csratio = K4B2G1646EBIH9_RATIO,
-	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
-	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
-	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
-	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
-	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
-	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
-};
-
-#define OSC    (V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
-		400, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr;
-}
-
-void set_uart_mux_conf(void)
-{
-	enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
-	enable_board_pin_mux();
-}
-
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
-	config_ddr(400, &ioregs, &ddr3_data,
-		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#endif
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	gpmc_init();
-
-	return 0;
-}
-
-#if defined(CONFIG_DRIVER_TI_CPSW)
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 0,
-		.phy_if		= PHY_INTERFACE_MODE_RMII,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-	int rv, ret = 0;
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-
-	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-
-	writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
-	       &cdev->miisel);
-
-	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
-		printf("Error %d registering CPSW switch\n", rv);
-	else
-		ret += rv;
-
-	return ret;
-}
-#endif
diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h
deleted file mode 100644
index a11d7ab..0000000
--- a/board/isee/igep0033/board.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * IGEP COM AQUILA boards information header
- *
- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * We must be able to enable uart0, for initial output. We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_board_pin_mux(void);
-#endif
diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c
deleted file mode 100644
index e862776..0000000
--- a/board/isee/igep0033/mux.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
-	{-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)},		/* MMC0_CD */
-	{-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{-1},
-};
-
-static struct module_pin_mux rmii1_pin_mux[] = {
-	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
-	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
-	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
-	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
-	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
-	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
-	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
-	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REF_CLK */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-/*
- * Do board-specific muxes.
- */
-void enable_board_pin_mux(void)
-{
-	/* NAND Flash */
-	configure_module_pin_mux(nand_pin_mux);
-	/* SD Card */
-	configure_module_pin_mux(mmc0_pin_mux);
-	/* Ethernet pinmux. */
-	configure_module_pin_mux(rmii1_pin_mux);
-}
diff --git a/board/isee/igep0046/MAINTAINERS b/board/isee/igep0046/MAINTAINERS
index aefd87b..be4801b 100644
--- a/board/isee/igep0046/MAINTAINERS
+++ b/board/isee/igep0046/MAINTAINERS
@@ -3,4 +3,4 @@ M:	Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
 S:	Maintained
 F:	board/isee/igep0046/igep0046.c
 F:	include/configs/igep0046.h
-F:	configs/mx6dl_igep0046_2G_defconfig
+F:	configs/mx6dl_igep0046_2G_defconfig
\ No newline at end of file
diff --git a/board/isee/igep0046/Makefile b/board/isee/igep0046/Makefile
index 6e521c9..b7d5f16 100644
--- a/board/isee/igep0046/Makefile
+++ b/board/isee/igep0046/Makefile
@@ -1,11 +1,12 @@
 #
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+# Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
 #
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Source file for IGEP0046 board
+#
+# Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y  += igep0046_eeprom.o
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
 obj-y  += igep0046.o
diff --git a/board/isee/igep0046/igep0046.c b/board/isee/igep0046/igep0046.c
index cdc0466..d3877d8 100644
--- a/board/isee/igep0046/igep0046.c
+++ b/board/isee/igep0046/igep0046.c
@@ -32,10 +32,12 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "pfuze.h"
-#include "igep0046_eeprom.h"
 #include "../common/igep_common.h"
+#include "../common/igep_eeprom.h"
+#include "../common/igep_test.h"
 #include <usb.h>
 #include <mmc.h>
+#include <net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -92,6 +94,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_LED_RED2		IMX_GPIO_NR(4, 20)
 #define GPIO_LED_GREEN2		IMX_GPIO_NR(4, 17)
 
+/* Define Revision */
+#define TEST_REVISION 4
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -187,11 +192,12 @@ static iomux_v3_cfg_t const init_pads[] =
 	MX6_PAD_CSI0_DAT7__GPIO5_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
 	#endif
 };
-#define STATION 0x01
-const uchar igep_mac0 [6] = { 0x02, 0xBA, 0xD0, 0xBA, 0xD0, STATION };
+#define STATION 0x02
+const uchar igep_mac0 [6] = { 0x02, 0xBA, 0xD0, 0xBB, 0xD1, STATION };
 uchar enetaddr[6];	
 static int igep_eeprom_valid = 0;
 static struct igep_mf_setup igep0046_eeprom_config;
+static int net_fail = 0;
 
 /* I2C MUX */
 #ifdef CONFIG_SYS_I2C
@@ -406,7 +412,9 @@ int board_eth_init(bd_t *bis)
 	get_mac_address();
 	setup_iomux_enet();
 #ifdef CONFIG_FEC_MXC
-	cpu_eth_init(bis);
+	if(cpu_eth_init(bis)){
+		net_fail = 1;
+	}
 #endif
 	return 0;
 }
@@ -421,19 +429,265 @@ int board_early_init_f(void)
 	setup_iomux_uart();
 
 	imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+	return 0;
+}
 
-	/* configure LEDS - SPL = 1 YELLOW */
-	gpio_direction_output(GPIO_LED_RED1, 1);
-	gpio_direction_output(GPIO_LED_GREEN1, 1);
+/* ------------- HERE IT WILL GO THE TEST FUNCTIONS THAT ITS EASIER TO BE HERE ------------- */
+
+void error_loop(int casee){
+
+	int su = 1;
+	/* Turn off LEDs */
+	gpio_direction_output(GPIO_LED_RED1, 0);
+	gpio_direction_output(GPIO_LED_GREEN1, 0);
 	gpio_direction_output(GPIO_LED_RED2, 0);
 	gpio_direction_output(GPIO_LED_GREEN2, 0);
+
+	switch (casee){
+		case 0:
+			/* I2C BUS ERROR */
+			/* Turn on LED combination to notify I2C FAILED */
+			/* We will infinite loop here 1 every 1 sec, combination is red-green switching every sec */
+			while(1){
+				if (su){
+					gpio_direction_output(GPIO_LED_RED1, 1);
+					gpio_direction_output(GPIO_LED_GREEN1, 0);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 1);
+					su=0;
+				}else{
+					gpio_direction_output(GPIO_LED_RED1, 0);
+					gpio_direction_output(GPIO_LED_GREEN1, 1);
+					gpio_direction_output(GPIO_LED_RED2, 1);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=1;
+				}
+				mdelay(500);
+			}
+			break;
+		case 1:
+			/* EEPROM ERROR */
+			while(1){
+				if (su){
+					gpio_direction_output(GPIO_LED_RED1, 1);
+					gpio_direction_output(GPIO_LED_GREEN1, 1);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=0;
+				}else{
+					gpio_direction_output(GPIO_LED_RED1, 0);
+					gpio_direction_output(GPIO_LED_GREEN1, 0);
+					gpio_direction_output(GPIO_LED_RED2, 1);
+					gpio_direction_output(GPIO_LED_GREEN2, 1);
+					su=1;
+				}
+				mdelay(500);
+			}
+			break;
+		case 2:
+			/* SDRAM ANY CHIP ERROR */
+			while(1){
+				if (su){
+					gpio_direction_output(GPIO_LED_RED1, 1);
+					gpio_direction_output(GPIO_LED_GREEN1, 1);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=0;
+				}else{
+					gpio_direction_output(GPIO_LED_RED1, 0);
+					gpio_direction_output(GPIO_LED_GREEN1, 0);
+					gpio_direction_output(GPIO_LED_RED2, 0);
+					gpio_direction_output(GPIO_LED_GREEN2, 0);
+					su=1;
+				}
+				mdelay(500);
+			}
+			break;
+	}
+}
+
+int test_i2c(void){
+
+	puts("Testing I2C...\n");
+	/* First we will test I2C */
+	if (setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1)){
+		puts("I2C: Bus 2 Error\n");
+		return 1;
+	}
+	if(setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2)){
+		puts("I2C: Bus 3 Error\n");
+		return 1;
+	}
+	mdelay(2);
 	return 0;
 }
 
-int board_init(void)
+uint8_t test_SDRAM(void)
+{
+	//dcache_disable();
+	int i = 0;
+	uint8_t result = 0;
+	uint64_t* file1 = 0;
+	uint64_t* file2 = 0;
+	uint64_t* file3 = 0;
+	uint64_t* file4 = 0;
+	int crc_value1 = 0;
+	int crc_value2 = 0;
+	int crc_value3 = 0;
+	int crc_value4 = 0;
+	int bytes = 1*1024*1024;
+
+	file1 = (uint64_t*) 0x20000000;
+	file2 = (uint64_t*) 0x40000000;
+	file3 = (uint64_t*) 0x60000000;
+	file4 = (uint64_t*) 0x80000000;
+
+/*
+	for(i=0; i<bytes;i++){
+		file1[i] = i%16;
+		file2[i] = i%16;
+		file3[i] = i%16;
+		file4[i] = i%16;
+	}
+*/
+	for(i=0; i<bytes;i++){
+		switch (i%6) {
+			case 0:
+				file1[i] = 0x0000AAAAULL;
+				file2[i] = (0x33330000ULL << 16);
+				file3[i] = (0x0000AAAAULL << 32);
+				file4[i] = (0x33330000ULL << 48);
+				break;
+			case 1:
+				file1[i] = 0x00005555ULL;
+				file2[i] = (0x99990000ULL << 16);
+				file3[i] = (0x00005555ULL << 32);
+				file4[i] = (0x99990000ULL << 48);
+				break;
+			case 2:
+				file1[i] = 0x0000CCCCULL;
+				file2[i] = (0x66660000ULL << 16);
+				file3[i] = (0x0000CCCCULL << 32);
+				file4[i] = (0x66660000ULL << 48);
+				break;
+			case 3:
+				file1[i] = 0x0000AAAAULL;
+				file2[i] = (0x33330000ULL << 16);
+				file3[i] = (0x0000AAAAULL << 32);
+				file4[i] = (0x00003333ULL << 48);
+				break;
+			case 4:
+				file1[i] = 0x00005555ULL;
+				file2[i] = (0x99990000ULL << 16);
+				file3[i] = (0x00005555ULL << 32);
+				file4[i] = (0x00009999ULL << 48);
+				break;
+			case 5:
+				file1[i] = 0x0000CCCCULL;
+				file2[i] = (0x66660000ULL << 16);
+				file3[i] = (0x0000CCCCULL << 32);
+				file4[i] = (0x66660000ULL << 48);
+				break;
+			default:
+				puts("Test RAM error \n");
+		}		
+	}
+
+	/* crc file 1 - CHIP 1 */
+	crc_value1 = crc32(0, (const unsigned char*) file1, bytes);
+	/* crc file 2 - CHIP 2 */
+	crc_value2 = crc32(0, (const unsigned char*) file2, bytes);
+	/* crc file 3 - CHIP 3 */
+	crc_value3 = crc32(0, (const unsigned char*) file3, bytes);
+	/* crc file 4 - CHIP 4 */
+	crc_value4 = crc32(0, (const unsigned char*) file4, bytes);
+
+  	printf("CHIP 1 U500 crc32: 0x%x \n", crc_value1);
+  	printf("CHIP 2 U501 crc32: 0x%x \n", crc_value2);
+ 	printf("CHIP 3 U502 crc32: 0x%x \n", crc_value3);
+  	printf("CHIP 4 U503 crc32: 0x%x \n", crc_value4);
+
+  	//dcache_enable();
+
+  	if(crc_value1 != KNOWN_CRC_CUSTOM_1MB_1){
+  		/* Chip 1 Fail */
+  		result = result + 0x01;
+  	}
+  	if(crc_value2 != KNOWN_CRC_CUSTOM_1MB_2){
+  		/* Chip 2 Fail */
+  		result = result + 0x02;
+  	}
+  	if(crc_value3 != KNOWN_CRC_CUSTOM_1MB_3){
+  		/* Chip 3 Fail */
+  		result = result + 0x04;
+  	}
+  	if(crc_value4 != KNOWN_CRC_CUSTOM_1MB_4){
+  		/* Chip 4 Fail */
+  		result = result + 0x08;
+  	}
+
+  	/* RESULT */
+  	return result;
+}
+
+int test_MMC(int who)
 {
+	struct mmc *mmc;
+
+	if(who){
+	/* eMMC case */
+	mmc = find_mmc_device(1);
+	}else{
+	/* SD case */
+	mmc = find_mmc_device(0);
+	}
+
+	if (!mmc){
+		return 1;
+	}
+
+	if (mmc_init(mmc)){
+		return 1;
+	}
 
-	/* configure LEDS - UBOOT = 2 YELLOW */
+	if (IS_SD(mmc)){
+		return 0;
+	}else{
+		return 0;
+	}
+	return 0;
+}
+
+int test_ETH(void)
+{
+	net_ping_ip = string_to_ip("192.168.2.171");
+	net_ip = string_to_ip("192.168.2.101");
+	net_netmask = string_to_ip("255.255.255.0");
+	net_gateway = string_to_ip("192.168.2.1");
+
+	/* Just to avoid warning */
+	if (net_ping_ip.s_addr == 0){
+		return CMD_RET_USAGE;
+	}
+
+	/* Check if network is already down */
+	if(net_fail){
+		return 1;
+	}
+	/*
+	else{
+		if (net_loop(5) < 0) {
+			printf("ping failed; host 192.168.2.171 is not alive\n");
+			return 1;
+		}
+	}
+	*/
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Configure LEDS - UBOOT = 2 YELLOW */
 	gpio_direction_output(GPIO_LED_RED1, 1);
 	gpio_direction_output(GPIO_LED_GREEN1, 1);
 	gpio_direction_output(GPIO_LED_RED2, 1);
@@ -456,7 +710,6 @@ int board_init(void)
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif
-
 	return 0;	
 }
 
@@ -491,46 +744,8 @@ static inline unsigned int pcb_version(void)
 }
 
 int board_late_init(void)
-{	
-
-	u32 crc_value = 0;
-	u32 crc_save_value;
-
-    if(check_eeprom() != 0){
-	printf("EEPROM: not found\n");
-    }else{
-		/* Read configuration from eeprom */
-		if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup)))
-	  		printf("EEPROM: read fail\n");	
-		/* Verify crc32 */
-
-	  	printf("EEPROM: read %d bytes \n", sizeof(struct igep_mf_setup));
-	  	printf("---------------------------- |!| IGEP STRUCT |!| ----------------------------\n");
-  		printf("magic_id: 0x%x \n", igep0046_eeprom_config.magic_id);
-  		printf("crc32: 0x%x \n", igep0046_eeprom_config.crc32);
-  		printf("board_uuid: %.36s \n", igep0046_eeprom_config.board_uuid);
-  		printf("board_pid: %.16s \n", igep0046_eeprom_config.board_pid);
-  		printf("model: %.8s \n", igep0046_eeprom_config.model);
-  		printf("variant: %.9s \n", igep0046_eeprom_config.variant);
-		printf("manf_of: %.6s \n", igep0046_eeprom_config.manf_of);
-  		printf("manf_timestamp: %.19s \n", igep0046_eeprom_config.manf_timestamp);
-		printf("bmac0: %.17s \n", igep0046_eeprom_config.bmac0);
-  		printf("bmac1: %.17s \n", igep0046_eeprom_config.bmac1);
-	  	printf("-----------------------------------------------------------------------------\n");
-
-
-	   	crc_save_value = igep0046_eeprom_config.crc32;
-	   	igep0046_eeprom_config.crc32 = 0;
-	   	crc_value = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
-  		printf("crc32 calculated: 0x%x \n", crc_value);
-		if(crc_save_value != crc_value){
-       		printf("EEPROM: CRC32 failed. Loading default MAC\n");				
-		}else{
-	    	printf("EEPROM: CRC32 OK! Loading MAC from eeprom\n");	       		
-	  		igep_eeprom_valid = 1;
-		}
-	}
-
+{
+	uint64_t cpuid = 0;
 	checkboard();
 	switch (pcb_version()) {
 		case PCB_REV_A:
@@ -570,8 +785,111 @@ int board_late_init(void)
 			setenv("fdt_file", "");
 			break;
 	}
+
+	/* Get CPU ID */
+	cpuid = ((uint64_t)readl(0x21bc420) << 32) | (readl(0x21bc410));
+	printf("CPU ID: 0x%llx \n",cpuid);
+	return 0;
+}
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void){
+	
+	/* This is the function that will be called last before running bootcmd u-boot */
+	uint16_t test = 0;
+	//uint8_t ramtest = 0;
+	uint64_t cpuid = 0;
+	
+	/* We need to read SPL eeprom struct to acquire whose test have already being done */
+	puts("---------------------------- |!| ISEE UBOOT TEST START |!| ----------------------------\n");
+	/* Get SPL last test */
+	test = load_test(SPL_MAGIC_ID_COUNTER);
+	if (test == 0x4000){
+		puts("SPL GET TEST FAILED.\n");
+
+	}else if (test == 0xfff0){
+		puts("I2C OK.\n");
+		puts("EEPROM OK.\n");
+		puts("POWER OK.\n");
+		puts("CPU OK.\n");
+		puts("SD OK.\n");
+		puts("REV OK.\n");
+		puts("IRAM OK.\n");
+		puts("SDRAM OK.\n");
+		puts("CPUID OK.\n");
+	}else{
+		puts("SOME SPL TEST FAILED, PERFORM MANUAL CHECK.\n");
+	}
+
+	/* Test RAM Now this will be done in SPL !!!
+	ramtest = test_SDRAM();
+
+	if((ramtest & 0x01) == 0x01){
+		puts("SDRAM CHIP 1 FAIL.\n");
+	}
+
+	if((ramtest & 0x02) == 0x02){
+		puts("SDRAM CHIP 2 FAIL.\n");
+	}
+
+	if((ramtest & 0x04) == 0x04){
+		puts("SDRAM CHIP 3 FAIL.\n");
+	}
+	
+	if((ramtest & 0x08) == 0x08){
+		puts("SDRAM CHIP 4 FAIL.\n");
+	}
+
+	if(!ramtest){
+		puts("RAM OK.\n");
+		test = test + 0xF0;
+	}else{
+		puts("RAM FAIL.\n");
+	}
+	*/
+
+	/* Test eMMC */
+	if(test_MMC(1)){
+		puts("eMMC FAIL.\n");
+	}else{
+		puts("eMMC OK.\n");
+		test = test + 0x08;
+	}
+
+	/* Test Ethernet */
+	if(test_ETH()){
+		puts("Ethernet FAIL.\n");
+	}else{
+		puts("Ethernet OK.\n");
+		test = test + 0x04;
+	}
+
+	/*
+	test_SATA();
+	test_USB();
+	*/
+	
+	/* We will reserve 2 bits for future test development like SATA, USB */
+	/* So for now add test the last 3 bits to 1 to forma a 0xffff if everything is ok */
+	test = test + 0x03;
+
+	/* Get CPU ID */
+	cpuid = ((uint64_t)readl(0x21bc420) << 32) | (readl(0x21bc410));
+	puts("CPUID OK.\n");
+
+	printf("U-BOOT Test Result: 0x%x\n",test);
+
+	/* Save Results to EEPROM */
+	if (save_test(test,UB_MAGIC_ID,cpuid)){
+		puts("ISEE U-BOOT TEST FAIL.\n");
+	}else{
+		puts("ISEE U-BOOT TEST OK.\n");
+	}
+
+	/* Let test process continue, bootcmd take us to kernel load via tftp and jump to it */
 	return 0;
 }
+#endif
 
 #ifdef CONFIG_LDO_BYPASS_CHECK
 /* TODO, use external pmic, for now always ldo_enable */
@@ -942,6 +1260,12 @@ void board_init_f(ulong dummy)
 	/* iomux and setup of UART and leds */
 	board_early_init_f();
 
+	/* configure LEDS - SPL = 1 YELLOW */
+	gpio_direction_output(GPIO_LED_RED1, 1);
+	gpio_direction_output(GPIO_LED_GREEN1, 1);
+	gpio_direction_output(GPIO_LED_RED2, 0);
+	gpio_direction_output(GPIO_LED_GREEN2, 0);
+
 	/* setup GP timer */
 	timer_init();
 
@@ -969,11 +1293,56 @@ void board_init_f(ulong dummy)
 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
 /* its our chance to print info about boot device */
 void spl_board_init(void)
-{
+{	
+	u32 boot_device = 0;
+	uint64_t cpuid = 0;
+	u16 test = 0;
+	uint8_t ramtest = 0;
 
-	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
-	u32 boot_device = spl_boot_device();
+	/* Minimal init sequence for pmic setup of igep imx6 boards */
+	#ifdef CONFIG_BASE0040
+	reset_audio();
+	#endif
 
+	/* First we will test I2C */
+	puts("---------------------------- |!| ISEE SPL TEST START |!| ----------------------------\n");
+
+	/* Test I2C */	
+	#ifdef CONFIG_SYS_I2C
+	if(test_i2c()){
+		puts("I2C FAIL.\n");
+		error_loop(0);
+	}else{
+		puts("I2C OK.\n");
+	}
+	#endif
+
+	/* Test EEPROM */
+	if(test_eeprom()){
+		puts("EEPROM FAIL.\n");
+		error_loop(1);
+	}else{
+		puts("EEPROM OK.\n");
+	}
+	mdelay(2);
+
+	/* If we are here we put test variable to 11000000 00000000 */ 
+	test = 0xC000;
+
+	/* Next we would want to know the counter just for control purpose */
+	//test_counter_check(SPL_TEST_COUNTER_OFF);
+
+	/* Test Power, PMIC */
+	if(power_init_board()){
+		puts("POWER FAIL.\n");
+	}else{
+		puts("POWER OK.\n");
+		/* Test = 11100000 00000000 */
+		test = test + 0x2000;
+	}
+
+	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
+	boot_device = spl_boot_device();
 	switch (boot_device) {
 	case BOOT_DEVICE_MMC1:
 		puts("Booting from MMC\n");
@@ -987,27 +1356,78 @@ void spl_board_init(void)
 	default:
 		puts("Unknown boot device\n");
 	}
+
+	/* If we are here (imx6) case CPU and SD should be working */
+	puts("CPU OK.\n");
+	puts("SD OK.\n");
+	/* Test = 11111000 00000000 */
+	test = test + 0x1800;
 	
-	/* Minimal init sequence for pmic setup of igep imx6 boards */
-	#ifdef CONFIG_BASE0040
-	reset_audio();
-	#endif
+	/* Test Revision PINs */
+	if (!(pcb_version() == TEST_REVISION)) {
+		puts("REV FAIL.\n");
+	}else{
+		puts("REV OK.\n");
+		/* Test = 11111100 00000000 */
+		test = test + 0x400;
+	}
 
-	#ifdef CONFIG_SYS_I2C
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-	mdelay(1);
-	#endif
+	/* Internal RAM is working */
+	puts("Internal RAM OK.\n");
+	/* Test = 11111110 00000000 */
+	test = test + 0x200;
+
+	/* Test SDRAM */
+	ramtest = test_SDRAM();
+
+	if((ramtest & 0x01) == 0x01){
+		puts("SDRAM CHIP 1 FAIL.\n");
+	}
+
+	if((ramtest & 0x02) == 0x02){
+		puts("SDRAM CHIP 2 FAIL.\n");
+	}
+
+	if((ramtest & 0x04) == 0x04){
+		puts("SDRAM CHIP 3 FAIL.\n");
+	}
+	
+	if((ramtest & 0x08) == 0x08){
+		puts("SDRAM CHIP 4 FAIL.\n");
+	}
+
+	if(!ramtest){
+		puts("SDRAM OK.\n");
+		test = test + 0xF0;
+	}else{
+		puts("SDRAM FAIL.\n");
+		/* Do not jump to UBOOT until SDRAM hardware is good */
+		error_loop(2);
+	}
+
+	/* Get CPU ID */
+	cpuid = ((uint64_t)readl(0x21bc420) << 32) | (readl(0x21bc410));
+	puts("CPUID OK.\n");
+	/* Test = 11111111 00000000 */
+	test = test + 0x100;
 
-	/* PMIC init */
-	power_init_board();
+	/* Print Test Result */
+	printf("SPL Test Result: 0x%x\n",test);
+
+	/* Save Results to EEPROM */
+	if (save_test(test,SPL_MAGIC_ID,cpuid)){
+		puts("ISEE SPL TEST FAIL.\n");
+	}else{
+		puts("ISEE SPL TEST OK.\n");
+	}
+	/* Jump to U-BOOT */
 }
 
 #ifdef CONFIG_SPL_OS_BOOT
-/* return 1 if we wish to boot to uboot vs os (falcon mode) */
+/* return 1 if we wish to boot to uboot vs 0 if we wish to falcon mode */
 int spl_start_uboot(void)
 {
-	return 0;
+	return 1;
 }
 
 void spl_board_prepare_for_linux(void)
@@ -1053,4 +1473,4 @@ void spl_board_prepare_for_linux(void)
 }
 
 #endif
-#endif
+#endif
\ No newline at end of file
diff --git a/board/isee/igep0046/igep0046_eeprom.c b/board/isee/igep0046/igep0046_eeprom.c
deleted file mode 100644
index d484d23..0000000
--- a/board/isee/igep0046/igep0046_eeprom.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
- *
- * EEPROM support source file for IGEP0046 board
- *
- * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/arch/sys_proto.h>
-
-
-int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size)
-{
-    u32 i;
-    u32 remain = size % 32;
-    u32 blocks = size / 32;
-    for (i=0; i < blocks; i++){
-        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
-            return -1;
-        }
-        udelay(5000);
-    }
-    if(remain > 0){
-        if(i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
-            return -1;
-        else
-            udelay(5000);
-    }
-    return 0;
-}
-
-int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size)
-{
-    u32 i;
-    u32 remain = size % 32;
-    u32 blocks = size / 32;
-    for (i=0; i < blocks; i++){
-        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), 32)){
-            return -1;
-        }
-    }
-    if(remain > 0)
-        if(i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, s_addr + (i*32), 2, (uint8_t*) data + (i*32), remain))
-            return -1;
-    return 0;
-}
-
-int check_eeprom (void)
-{
-    i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS);
-    /* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		printf("Could not probe the EEPROM at 0x%x\n",
-		       CONFIG_SYS_I2C_EEPROM_ADDR);
-		return -1;
-	}
-	return 0;
-}
-
-unsigned int parse_char(char c)
-{
-    if ('0' <= c && c <= '9') return c - '0';
-    if ('a' <= c && c <= 'f') return 10 + c - 'a';
-    if ('A' <= c && c <= 'F') return 10 + c - 'A';
-    
-    return 0;
-}
\ No newline at end of file
diff --git a/board/isee/igep0046/igep0046_eeprom.h b/board/isee/igep0046/igep0046_eeprom.h
deleted file mode 100644
index df739e0..0000000
--- a/board/isee/igep0046/igep0046_eeprom.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
- *
- * 0046 EEPROM Definitions
- *
- * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __EEPROM_BOARD_HELPER__
-#define __EEPROM_BOARD_HELPER__
-
-int eeprom46_write_setup (uint8_t s_addr, const char* data, u32 size);
-int eeprom46_read_setup (uint8_t s_addr, char* data, u32 size);
-int check_eeprom (void);
-unsigned int parse_char(char c);
-#endif
diff --git a/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg b/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
index 21e319f..9dc1d8d 100644
--- a/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
+++ b/board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg
@@ -1,204 +1,203 @@
-/*

- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz

- *

- * SPDX-License-Identifier:	GPL-2.0+

- *

- * Refer docs/README.imxmage for more details about how-to configure

- * and create imximage boot image

- *

- * The syntax is taken as close as possible with the kwbimage

- */

-

-/* image version */

-

-IMAGE_VERSION 2

-

-/*

- * Boot Device : one of

- * spi, sd (the board has no nand neither onenand)

- */

-

-BOOT_FROM	sd

-

-/*

- * Device Configuration Data (DCD)

- *

- * Each entry must have the format:

- * Addr-type           Address        Value

- *

- * where:

- *	Addr-type register length (1,2 or 4	bytes)

- *	Address	  absolute address of the register

- *	value	  value to be stored in the register

- */

-

-//=============================================================================			

-// Enable all clocks (they are disabled by ROM code)			

-//=============================================================================			

-DATA 4	0x020c4068 0xffffffff	

-DATA 4	0x020c406c 0xffffffff	

-DATA 4	0x020c4070 0xffffffff	

-DATA 4	0x020c4074 0xffffffff	

-DATA 4	0x020c4078 0xffffffff	

-DATA 4	0x020c407c 0xffffffff	

-DATA 4	0x020c4080 0xffffffff	

-DATA 4	0x020c4084 0xffffffff	

-			

-//=============================================================================			

-// IOMUX			

-//=============================================================================			

-//DDR IO TYPE:			

-DATA 4	0x020e0774 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 

-DATA 4	0x020e0754 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE 

-			

-//CLOCK:			

-DATA 4	0x020e04ac 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0

-DATA 4	0x020e04b0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

-			

-//ADDRESS:			

-DATA 4	0x020e0464 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

-DATA 4	0x020e0490 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

-DATA 4	0x020e074c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS 

-			

-//Control:			

-DATA 4	0x020e0494 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET

-DATA 4	0x020e04a0 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

-DATA 4	0x020e04b4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

-DATA 4	0x020e04b8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

-DATA 4	0x020e076c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS 

-			

-//Data Strobes:			

-DATA 4	0x020e0750 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 

-DATA 4	0x020e04bc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 

-DATA 4	0x020e04c0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 

-DATA 4	0x020e04c4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 

-DATA 4	0x020e04c8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 

-DATA 4	0x020e04cc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 

-DATA 4	0x020e04d0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 

-DATA 4	0x020e04d4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 

-DATA 4	0x020e04d8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 

-			

-//Data:			

-DATA 4	0x020e0760 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE

-DATA 4	0x020e0764 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS 

-DATA 4	0x020e0770 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS 

-DATA 4	0x020e0778 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B2DS 

-DATA 4	0x020e077c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B3DS 

-DATA 4	0x020e0780 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B4DS 

-DATA 4	0x020e0784 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B5DS 

-DATA 4	0x020e078c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B6DS 

-DATA 4	0x020e0748 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B7DS 

-			

-DATA 4	0x020e0470 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

-DATA 4	0x020e0474 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

-DATA 4	0x020e0478 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2

-DATA 4	0x020e047c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

-DATA 4	0x020e0480 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4

-DATA 4	0x020e0484 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5

-DATA 4	0x020e0488 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6

-DATA 4	0x020e048c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7

-			

-			

-//=============================================================================			

-// DDR Controller Registers			

-//=============================================================================			

-// Manufacturer:	Samsung		

-// Device Part Number:	K4B4G1646D-BMK00CV		

-// Clock Freq.: 	MHz		

-// Density per CS in Gb: 	16		

-// Chip Selects used:	1		

-// Number of Banks:	8		

-// Row address:    	15		

-// Column address: 	10		

-// Data bus width	64		

-//=============================================================================			

-DATA 4	0x021b001c 0x00008000	MMDC0_MDSCR, set the Configuration request bit during MMDC set up

-			

-//=============================================================================			

-// Calibration setup.			

-//=============================================================================			

-DATA 4	0x021b0800 0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

-			

-// For target board, may need to run write leveling calibration to fine tune these settings.			

-DATA 4	0x021b080c 0x00530056	

-DATA 4	0x021b0810 0x00440053	

-DATA 4	0x021b480c 0x002B002B	

-DATA 4	0x021b4810 0x0028003F	

-			

-////Read DQS Gating calibration			

-DATA 4	0x021b083c 0x021C021C	// MPDGCTRL0 PHY0

-DATA 4	0x021b0840 0x02140214	// MPDGCTRL1 PHY0

-DATA 4	0x021b483c 0x0178017C	// MPDGCTRL0 PHY1

-DATA 4	0x021b4840 0x016C0170	// MPDGCTRL1 PHY1

-			

-//Read calibration			

-DATA 4	0x021b0848 0x46484C48	// MPRDDLCTL PHY0

-DATA 4	0x021b4848 0x42424842	// MPRDDLCTL PHY1

-			

-//Write calibration                     			

-DATA 4	0x021b0850 0x3434302E	// MPWRDLCTL PHY0

-DATA 4	0x021b4850 0x3A303830	// MPWRDLCTL PHY1

-			

-//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)			

-DATA 4	0x021b081c 0x33333333	// DDR_PHY_P0_MPREDQBY0DL3

-DATA 4	0x021b0820 0x33333333	// DDR_PHY_P0_MPREDQBY1DL3

-DATA 4	0x021b0824 0x33333333	// DDR_PHY_P0_MPREDQBY2DL3

-DATA 4	0x021b0828 0x33333333	// DDR_PHY_P0_MPREDQBY3DL3

-DATA 4	0x021b481c 0x33333333	// DDR_PHY_P1_MPREDQBY0DL3

-DATA 4	0x021b4820 0x33333333	// DDR_PHY_P1_MPREDQBY1DL3

-DATA 4	0x021b4824 0x33333333	// DDR_PHY_P1_MPREDQBY2DL3

-DATA 4	0x021b4828 0x33333333	// DDR_PHY_P1_MPREDQBY3DL3

-			

-//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented			

-//DATA 4	0x021b08c0 0x24911492	// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6

-//DATA 4	0x021b48c0 0x24911492	

-			

-// Complete calibration by forced measurement:                  			

-DATA 4	0x021b08b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr

-DATA 4	0x021b48b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr

-//=============================================================================			

-// Calibration setup end			

-//=============================================================================			

-			

-//MMDC init: 			

-DATA 4	0x021b0004 0x0002002D	// MMDC0_MDPDC

-DATA 4	0x021b0008 0x00333040	// MMDC0_MDOTC

-DATA 4	0x021b000c 0x676B52F3	// MMDC0_MDCFG0

-DATA 4	0x021b0010 0xB66D8B63	// MMDC0_MDCFG1

-DATA 4	0x021b0014 0x01FF00DB	// MMDC0_MDCFG2

-			

-//MDMISC: RALAT kept to the high level of 5. 			

-//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 			

-//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			

-//b. Small performence improvment 			

-DATA 4	0x021b0018 0x00011740	// MMDC0_MDMISC

-DATA 4	0x021b001c 0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up

-DATA 4	0x021b002c 0x000026D2	// MMDC0_MDRWD

-DATA 4	0x021b0030 0x006B1023	// MMDC0_MDOR

-DATA 4	0x021b0040 0x00000047	// Chan0 CS0_END 

-DATA 4	0x021b0000 0x841A0000	// MMDC0_MDCTL

-			

-//Mode register writes                 			

-DATA 4	0x021b001c 0x02008032	// MMDC0_MDSCR, MR2 write, CS0

-DATA 4	0x021b001c 0x00008033	// MMDC0_MDSCR, MR3 write, CS0

-DATA 4	0x021b001c 0x00048031	// MMDC0_MDSCR, MR1 write, CS0

-DATA 4	0x021b001c 0x15208030	// MMDC0_MDSCR, MR0write, CS0

-DATA 4	0x021b001c 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0

-			

-//DATA 4	0x021b001c 0x0200803A	// MMDC0_MDSCR, MR2 write, CS1

-//DATA 4	0x021b001c 0x0000803B	// MMDC0_MDSCR, MR3 write, CS1

-//DATA 4	0x021b001c 0x00048039	// MMDC0_MDSCR, MR1 write, CS1

-//DATA 4	0x021b001c 0x15208038	// MMDC0_MDSCR, MR0write, CS1

-//DATA 4	0x021b001c 0x04008048	// MMDC0_MDSCR, ZQ calibration command sent to device on CS1

-			

-DATA 4	0x021b0020 0x00007800	// MMDC0_MDREF

-			

-DATA 4	0x021b0818 0x00022227	// DDR_PHY_P0_MPODTCTRL

-DATA 4	0x021b4818 0x00022227	// DDR_PHY_P1_MPODTCTRL

-			

-DATA 4	0x021b0004 0x0002556D	// MMDC0_MDPDC now SDCTL power down enabled

-			

-DATA 4	0x021b0404 0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

-			

-DATA 4	0x021b001c 0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

-

+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4	bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+//=============================================================================			
+// Enable all clocks (they are disabled by ROM code)			
+//=============================================================================			
+DATA 4	0x020c4068 0xffffffff	
+DATA 4	0x020c406c 0xffffffff	
+DATA 4	0x020c4070 0xffffffff	
+DATA 4	0x020c4074 0xffffffff	
+DATA 4	0x020c4078 0xffffffff	
+DATA 4	0x020c407c 0xffffffff	
+DATA 4	0x020c4080 0xffffffff	
+DATA 4	0x020c4084 0xffffffff	
+			
+//=============================================================================			
+// IOMUX			
+//=============================================================================			
+//DDR IO TYPE:			
+DATA 4	0x020e0774 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 
+DATA 4	0x020e0754 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE 
+			
+//CLOCK:			
+DATA 4	0x020e04ac 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
+DATA 4	0x020e04b0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
+			
+//ADDRESS:			
+DATA 4	0x020e0464 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
+DATA 4	0x020e0490 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
+DATA 4	0x020e074c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS 
+			
+//Control:			
+DATA 4	0x020e0494 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
+DATA 4	0x020e04a0 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
+DATA 4	0x020e04b4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+DATA 4	0x020e04b8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+DATA 4	0x020e076c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS 
+			
+//Data Strobes:			
+DATA 4	0x020e0750 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 
+DATA 4	0x020e04bc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 
+DATA 4	0x020e04c0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 
+DATA 4	0x020e04c4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 
+DATA 4	0x020e04c8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 
+DATA 4	0x020e04cc 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 
+DATA 4	0x020e04d0 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 
+DATA 4	0x020e04d4 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 
+DATA 4	0x020e04d8 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 
+			
+//Data:			
+DATA 4	0x020e0760 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
+DATA 4	0x020e0764 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS 
+DATA 4	0x020e0770 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS 
+DATA 4	0x020e0778 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B2DS 
+DATA 4	0x020e077c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B3DS 
+DATA 4	0x020e0780 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B4DS 
+DATA 4	0x020e0784 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B5DS 
+DATA 4	0x020e078c 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B6DS 
+DATA 4	0x020e0748 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B7DS 
+			
+DATA 4	0x020e0470 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
+DATA 4	0x020e0474 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
+DATA 4	0x020e0478 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
+DATA 4	0x020e047c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
+DATA 4	0x020e0480 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4
+DATA 4	0x020e0484 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5
+DATA 4	0x020e0488 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6
+DATA 4	0x020e048c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7
+			
+			
+//=============================================================================			
+// DDR Controller Registers			
+//=============================================================================			
+// Manufacturer:	Samsung		
+// Device Part Number:	K4B4G1646D-BMK00CV		
+// Clock Freq.: 	MHz		
+// Density per CS in Gb: 	16		
+// Chip Selects used:	1		
+// Number of Banks:	8		
+// Row address:    	15		
+// Column address: 	10		
+// Data bus width	64		
+//=============================================================================			
+DATA 4	0x021b001c 0x00008000	MMDC0_MDSCR, set the Configuration request bit during MMDC set up
+			
+//=============================================================================			
+// Calibration setup.			
+//=============================================================================			
+DATA 4	0x021b0800 0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
+			
+// For target board, may need to run write leveling calibration to fine tune these settings.			
+DATA 4	0x021b080c 0x00530056	
+DATA 4	0x021b0810 0x00440053	
+DATA 4	0x021b480c 0x002B002B	
+DATA 4	0x021b4810 0x0028003F	
+			
+////Read DQS Gating calibration			
+DATA 4	0x021b083c 0x021C021C	// MPDGCTRL0 PHY0
+DATA 4	0x021b0840 0x02140214	// MPDGCTRL1 PHY0
+DATA 4	0x021b483c 0x0178017C	// MPDGCTRL0 PHY1
+DATA 4	0x021b4840 0x016C0170	// MPDGCTRL1 PHY1
+			
+//Read calibration			
+DATA 4	0x021b0848 0x46484C48	// MPRDDLCTL PHY0
+DATA 4	0x021b4848 0x42424842	// MPRDDLCTL PHY1
+			
+//Write calibration                     			
+DATA 4	0x021b0850 0x3434302E	// MPWRDLCTL PHY0
+DATA 4	0x021b4850 0x3A303830	// MPWRDLCTL PHY1
+			
+//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)			
+DATA 4	0x021b081c 0x33333333	// DDR_PHY_P0_MPREDQBY0DL3
+DATA 4	0x021b0820 0x33333333	// DDR_PHY_P0_MPREDQBY1DL3
+DATA 4	0x021b0824 0x33333333	// DDR_PHY_P0_MPREDQBY2DL3
+DATA 4	0x021b0828 0x33333333	// DDR_PHY_P0_MPREDQBY3DL3
+DATA 4	0x021b481c 0x33333333	// DDR_PHY_P1_MPREDQBY0DL3
+DATA 4	0x021b4820 0x33333333	// DDR_PHY_P1_MPREDQBY1DL3
+DATA 4	0x021b4824 0x33333333	// DDR_PHY_P1_MPREDQBY2DL3
+DATA 4	0x021b4828 0x33333333	// DDR_PHY_P1_MPREDQBY3DL3
+			
+//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented			
+//DATA 4	0x021b08c0 0x24911492	// fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
+//DATA 4	0x021b48c0 0x24911492	
+			
+// Complete calibration by forced measurement:                  			
+DATA 4	0x021b08b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr
+DATA 4	0x021b48b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr
+//=============================================================================			
+// Calibration setup end			
+//=============================================================================			
+			
+//MMDC init: 			
+DATA 4	0x021b0004 0x0002002D	// MMDC0_MDPDC
+DATA 4	0x021b0008 0x00333040	// MMDC0_MDOTC
+DATA 4	0x021b000c 0x676B52F3	// MMDC0_MDCFG0
+DATA 4	0x021b0010 0xB66D8B63	// MMDC0_MDCFG1
+DATA 4	0x021b0014 0x01FF00DB	// MMDC0_MDCFG2
+			
+//MDMISC: RALAT kept to the high level of 5. 			
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 			
+//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			
+//b. Small performence improvment 			
+DATA 4	0x021b0018 0x00011740	// MMDC0_MDMISC
+DATA 4	0x021b001c 0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up
+DATA 4	0x021b002c 0x000026D2	// MMDC0_MDRWD
+DATA 4	0x021b0030 0x006B1023	// MMDC0_MDOR
+DATA 4	0x021b0040 0x00000047	// Chan0 CS0_END 
+DATA 4	0x021b0000 0x841A0000	// MMDC0_MDCTL
+			
+//Mode register writes                 			
+DATA 4	0x021b001c 0x02008032	// MMDC0_MDSCR, MR2 write, CS0
+DATA 4	0x021b001c 0x00008033	// MMDC0_MDSCR, MR3 write, CS0
+DATA 4	0x021b001c 0x00048031	// MMDC0_MDSCR, MR1 write, CS0
+DATA 4	0x021b001c 0x15208030	// MMDC0_MDSCR, MR0write, CS0
+DATA 4	0x021b001c 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0
+			
+//DATA 4	0x021b001c 0x0200803A	// MMDC0_MDSCR, MR2 write, CS1
+//DATA 4	0x021b001c 0x0000803B	// MMDC0_MDSCR, MR3 write, CS1
+//DATA 4	0x021b001c 0x00048039	// MMDC0_MDSCR, MR1 write, CS1
+//DATA 4	0x021b001c 0x15208038	// MMDC0_MDSCR, MR0write, CS1
+//DATA 4	0x021b001c 0x04008048	// MMDC0_MDSCR, ZQ calibration command sent to device on CS1
+			
+DATA 4	0x021b0020 0x00007800	// MMDC0_MDREF
+			
+DATA 4	0x021b0818 0x00022227	// DDR_PHY_P0_MPODTCTRL
+DATA 4	0x021b4818 0x00022227	// DDR_PHY_P1_MPODTCTRL
+			
+DATA 4	0x021b0004 0x0002556D	// MMDC0_MDPDC now SDCTL power down enabled
+			
+DATA 4	0x021b0404 0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.
+			
+DATA 4	0x021b001c 0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)
\ No newline at end of file
diff --git a/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg b/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
index dd10a58..926c1d5 100644
--- a/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
+++ b/board/isee/igep0046/mx6q_igep0046_4x512_nt.cfg
@@ -1,142 +1,142 @@
-/*

- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz

- *

- * SPDX-License-Identifier:	GPL-2.0+

- *

- * Refer docs/README.imxmage for more details about how-to configure

- * and create imximage boot image

- *

- * The syntax is taken as close as possible with the kwbimage

- */

-

-/* image version */

-

-IMAGE_VERSION 2

-

-/*

- * Boot Device : one of

- * spi, sd (the board has no nand neither onenand)

- */

-

-BOOT_FROM	sd

-

-/*

- * Device Configuration Data (DCD)

- *

- * Each entry must have the format:

- * Addr-type           Address        Value

- *

- * where:

- *	Addr-type register length (1,2 or 4 bytes)

- *	Address	  absolute address of the register

- *	value	  value to be stored in the register

- */

-DATA 4, 0x020e0798, 0x000C0000

-DATA 4, 0x020e0758, 0x00000000

-DATA 4, 0x020e0588, 0x00020030

-DATA 4, 0x020e0594, 0x00020030

-DATA 4, 0x020e056c, 0x00020030

-DATA 4, 0x020e0578, 0x00020030

-DATA 4, 0x020e074c, 0x00000030

-DATA 4, 0x020e057c, 0x00020030

-DATA 4, 0x020e058c, 0x00000000

-DATA 4, 0x020e059c, 0x00003030

-DATA 4, 0x020e05a0, 0x00003030

-DATA 4, 0x020e078c, 0x00000030

-DATA 4, 0x020e0750, 0x00020000

-DATA 4, 0x020e05a8, 0x00000030

-DATA 4, 0x020e05b0, 0x00000030

-DATA 4, 0x020e0524, 0x00000030

-DATA 4, 0x020e051c, 0x00000030

-DATA 4, 0x020e0518, 0x00000030

-DATA 4, 0x020e050c, 0x00000030

-DATA 4, 0x020e05b8, 0x00000030

-DATA 4, 0x020e05c0, 0x00000030

-DATA 4, 0x020e0774, 0x00020000

-DATA 4, 0x020e0784, 0x00000030

-DATA 4, 0x020e0788, 0x00000030

-DATA 4, 0x020e0794, 0x00000030

-DATA 4, 0x020e079c, 0x00000030

-DATA 4, 0x020e07a0, 0x00000030

-DATA 4, 0x020e07a4, 0x00000030

-DATA 4, 0x020e07a8, 0x00000030

-DATA 4, 0x020e0748, 0x00000030

-DATA 4, 0x020e05ac, 0x00020030

-DATA 4, 0x020e05b4, 0x00020030

-DATA 4, 0x020e0528, 0x00020030

-DATA 4, 0x020e0520, 0x00020030

-DATA 4, 0x020e0514, 0x00020030

-DATA 4, 0x020e0510, 0x00020030

-DATA 4, 0x020e05bc, 0x00020030

-DATA 4, 0x020e05c4, 0x00020030

-DATA 4, 0x021b0800, 0xa1390003

-DATA 4, 0x021b080c, 0x001F001F

-DATA 4, 0x021b0810, 0x001F001F

-DATA 4, 0x021b480c, 0x001F001F

-DATA 4, 0x021b4810, 0x001F001F

-DATA 4, 0x021b083c, 0x43270338

-DATA 4, 0x021b0840, 0x03200314

-DATA 4, 0x021b483c, 0x431A032F

-DATA 4, 0x021b4840, 0x03200263

-DATA 4, 0x021b0848, 0x4B434748

-DATA 4, 0x021b4848, 0x4445404C

-DATA 4, 0x021b0850, 0x38444542

-DATA 4, 0x021b4850, 0x4935493A

-DATA 4, 0x021b081c, 0x33333333

-DATA 4, 0x021b0820, 0x33333333

-DATA 4, 0x021b0824, 0x33333333

-DATA 4, 0x021b0828, 0x33333333

-DATA 4, 0x021b481c, 0x33333333

-DATA 4, 0x021b4820, 0x33333333

-DATA 4, 0x021b4824, 0x33333333

-DATA 4, 0x021b4828, 0x33333333

-DATA 4, 0x021b08b8, 0x00000800

-DATA 4, 0x021b48b8, 0x00000800

-DATA 4, 0x021b0004, 0x00020036

-DATA 4, 0x021b0008, 0x09444040

-DATA 4, 0x021b000c, 0x898E7974

-DATA 4, 0x021b0010, 0xDB538F64

-DATA 4, 0x021b0014, 0x01FF00DB

-DATA 4, 0x021b0018, 0x00081740

-DATA 4, 0x021b001c, 0x00008000

-DATA 4, 0x021b002c, 0x000026d2

-DATA 4, 0x021b0030, 0x008E1023

-DATA 4, 0x021b0040, 0x00000047

-DATA 4, 0x021b0000, 0x841A0000

-DATA 4, 0x021b001c, 0x04088032

-DATA 4, 0x021b001c, 0x00008033

-DATA 4, 0x021b001c, 0x00428031

-DATA 4, 0x021b001c, 0x19308030

-DATA 4, 0x021b001c, 0x04008040

-DATA 4, 0x021b0020, 0x00007800

-DATA 4, 0x021b0818, 0x00022227

-DATA 4, 0x021b4818, 0x00022227

-DATA 4, 0x021b0004, 0x00025576

-DATA 4, 0x021b0404, 0x00011006

-DATA 4, 0x021b001c, 0x00000000

-

-/* set the default clock gate to save power */

-DATA 4, 0x020c4068, 0x00C03F3F

-DATA 4, 0x020c406c, 0x0030FC03

-DATA 4, 0x020c4070, 0x0FFFC000

-DATA 4, 0x020c4074, 0x3FF00000

-DATA 4, 0x020c4078, 0x00FFF300

-DATA 4, 0x020c407c, 0x0F0000F3

-DATA 4, 0x020c4080, 0x000003FF

-

-/* enable AXI cache for VDOA/VPU/IPU */

-DATA 4, 0x020e0010, 0xF00000CF

-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */

-DATA 4, 0x020e0018, 0x007F007F

-DATA 4, 0x020e001c, 0x007F007F

-

-/*

- * Setup CCM_CCOSR register as follows:

- *

- * cko1_en  = 1	   --> CKO1 enabled

- * cko1_div = 111  --> divide by 8

- * cko1_sel = 1011 --> ahb_clk_root

- *

- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz

- */

-DATA 4, 0x020c4060, 0x000000fb

+/*
+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4, 0x020e0798, 0x000C0000
+DATA 4, 0x020e0758, 0x00000000
+DATA 4, 0x020e0588, 0x00020030
+DATA 4, 0x020e0594, 0x00020030
+DATA 4, 0x020e056c, 0x00020030
+DATA 4, 0x020e0578, 0x00020030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e057c, 0x00020030
+DATA 4, 0x020e058c, 0x00000000
+DATA 4, 0x020e059c, 0x00003030
+DATA 4, 0x020e05a0, 0x00003030
+DATA 4, 0x020e078c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e05a8, 0x00000030
+DATA 4, 0x020e05b0, 0x00000030
+DATA 4, 0x020e0524, 0x00000030
+DATA 4, 0x020e051c, 0x00000030
+DATA 4, 0x020e0518, 0x00000030
+DATA 4, 0x020e050c, 0x00000030
+DATA 4, 0x020e05b8, 0x00000030
+DATA 4, 0x020e05c0, 0x00000030
+DATA 4, 0x020e0774, 0x00020000
+DATA 4, 0x020e0784, 0x00000030
+DATA 4, 0x020e0788, 0x00000030
+DATA 4, 0x020e0794, 0x00000030
+DATA 4, 0x020e079c, 0x00000030
+DATA 4, 0x020e07a0, 0x00000030
+DATA 4, 0x020e07a4, 0x00000030
+DATA 4, 0x020e07a8, 0x00000030
+DATA 4, 0x020e0748, 0x00000030
+DATA 4, 0x020e05ac, 0x00020030
+DATA 4, 0x020e05b4, 0x00020030
+DATA 4, 0x020e0528, 0x00020030
+DATA 4, 0x020e0520, 0x00020030
+DATA 4, 0x020e0514, 0x00020030
+DATA 4, 0x020e0510, 0x00020030
+DATA 4, 0x020e05bc, 0x00020030
+DATA 4, 0x020e05c4, 0x00020030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001F001F
+DATA 4, 0x021b0810, 0x001F001F
+DATA 4, 0x021b480c, 0x001F001F
+DATA 4, 0x021b4810, 0x001F001F
+DATA 4, 0x021b083c, 0x43270338
+DATA 4, 0x021b0840, 0x03200314
+DATA 4, 0x021b483c, 0x431A032F
+DATA 4, 0x021b4840, 0x03200263
+DATA 4, 0x021b0848, 0x4B434748
+DATA 4, 0x021b4848, 0x4445404C
+DATA 4, 0x021b0850, 0x38444542
+DATA 4, 0x021b4850, 0x4935493A
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x33333333
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x09444040
+DATA 4, 0x021b000c, 0x898E7974
+DATA 4, 0x021b0010, 0xDB538F64
+DATA 4, 0x021b0014, 0x01FF00DB
+DATA 4, 0x021b0018, 0x00081740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x008E1023
+DATA 4, 0x021b0040, 0x00000047
+DATA 4, 0x021b0000, 0x841A0000
+DATA 4, 0x021b001c, 0x04088032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00428031
+DATA 4, 0x021b001c, 0x19308030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00007800
+DATA 4, 0x021b0818, 0x00022227
+DATA 4, 0x021b4818, 0x00022227
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFC000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, 0x020c4060, 0x000000fb
\ No newline at end of file
diff --git a/board/isee/igep0046/pfuze.c b/board/isee/igep0046/pfuze.c
index d6a209e..e3aa89f 100644
--- a/board/isee/igep0046/pfuze.c
+++ b/board/isee/igep0046/pfuze.c
@@ -89,4 +89,4 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
 	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 
 	return p;
-}
+}
\ No newline at end of file
diff --git a/board/isee/igep0046/pfuze.h b/board/isee/igep0046/pfuze.h
index 53cfc99..131c7cc 100644
--- a/board/isee/igep0046/pfuze.h
+++ b/board/isee/igep0046/pfuze.h
@@ -10,4 +10,4 @@
 struct pmic *pfuze_common_init(unsigned char i2cbus);
 int pfuze_mode_init(struct pmic *p, u32 mode);
 
-#endif
+#endif
\ No newline at end of file
diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig
deleted file mode 100644
index aa46882..0000000
--- a/board/isee/igep00x0/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP3_IGEP00X0
-
-config SYS_BOARD
-	default "igep00x0"
-
-config SYS_VENDOR
-	default "isee"
-
-config SYS_CONFIG_NAME
-	default "omap3_igep00x0"
-
-endif
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
deleted file mode 100644
index 720ef2a..0000000
--- a/board/isee/igep00x0/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-IGEP00X0 BOARD
-M:	Enric Balletbo i Serra <eballetbo@gmail.com>
-S:	Maintained
-F:	board/isee/igep00x0/
-F:	include/configs/omap3_igep00x0.h
-F:	configs/igep0020_defconfig
-F:	configs/igep0030_defconfig
-F:	configs/igep0032_defconfig
diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
deleted file mode 100644
index 68b151c..0000000
--- a/board/isee/igep00x0/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= igep00x0.o
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
deleted file mode 100644
index 65cc7df..0000000
--- a/board/isee/igep00x0/igep00x0.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <status_led.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <twl4030.h>
-#include <netdev.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/onenand.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <fdt_support.h>
-#include "igep00x0.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static const struct ns16550_platdata igep_serial = {
-	.base = OMAP34XX_UART3,
-	.reg_shift = 2,
-	.clock = V_NS16550_CLK,
-	.fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(igep_uart) = {
-	"ns16550_serial",
-	&igep_serial
-};
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	int loops = 100;
-
-	/* find out flash memory type, assume NAND first */
-	gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
-	gpmc_init();
-
-	/* Issue a RESET and then READID */
-	writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
-	writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
-	while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
-	                                        != NAND_STATUS_READY) {
-		udelay(1);
-		if (--loops == 0) {
-			gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
-			gpmc_init();	/* reinitialize for OneNAND */
-			break;
-		}
-	}
-
-	/* boot param addr */
-	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
-	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
-	int mfr, id, err = identify_nand_chip(&mfr, &id);
-
-	timings->mr = MICRON_V_MR_165;
-	if (!err) {
-		switch (mfr) {
-		case NAND_MFR_HYNIX:
-			timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
-			timings->ctrla = HYNIX_V_ACTIMA_200;
-			timings->ctrlb = HYNIX_V_ACTIMB_200;
-			break;
-		case NAND_MFR_MICRON:
-			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
-			timings->ctrla = MICRON_V_ACTIMA_200;
-			timings->ctrlb = MICRON_V_ACTIMB_200;
-			break;
-		default:
-			/* Should not happen... */
-			break;
-		}
-		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-		gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
-	} else {
-		if (get_cpu_family() == CPU_OMAP34XX) {
-			timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
-			timings->ctrla = NUMONYX_V_ACTIMA_165;
-			timings->ctrlb = NUMONYX_V_ACTIMB_165;
-			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-		} else {
-			timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
-			timings->ctrla = NUMONYX_V_ACTIMA_200;
-			timings->ctrlb = NUMONYX_V_ACTIMB_200;
-			timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-		}
-		gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
-	}
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
-	/* break into full u-boot on 'c' */
-	if (serial_tstc() && serial_getc() == 'c')
-		return 1;
-
-	return 0;
-}
-#endif
-#endif
-
-int onenand_board_init(struct mtd_info *mtd)
-{
-	if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
-		struct onenand_chip *this = mtd->priv;
-		this->base = (void *)CONFIG_SYS_ONENAND_BASE;
-		return 0;
-	}
-	return 1;
-}
-
-#if defined(CONFIG_CMD_NET)
-static void reset_net_chip(int gpio)
-{
-	if (!gpio_request(gpio, "eth nrst")) {
-		gpio_direction_output(gpio, 1);
-		udelay(1);
-		gpio_set_value(gpio, 0);
-		udelay(40);
-		gpio_set_value(gpio, 1);
-		mdelay(10);
-	}
-}
-
-/*
- * Routine: setup_net_chip
- * Description: Setting up the configuration GPMC registers specific to the
- *		Ethernet hardware.
- */
-static void setup_net_chip(void)
-{
-	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-	static const u32 gpmc_lan_config[] = {
-		NET_LAN9221_GPMC_CONFIG1,
-		NET_LAN9221_GPMC_CONFIG2,
-		NET_LAN9221_GPMC_CONFIG3,
-		NET_LAN9221_GPMC_CONFIG4,
-		NET_LAN9221_GPMC_CONFIG5,
-		NET_LAN9221_GPMC_CONFIG6,
-	};
-
-	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
-			CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
-
-	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
-	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
-	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
-		&ctrl_base->gpmc_nadv_ale);
-
-	reset_net_chip(64);
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SMC911X
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#else
-	return 0;
-#endif
-}
-#else
-static inline void setup_net_chip(void) {}
-#endif
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
-	return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_GENERIC_MMC)
-void board_mmc_power_init(void)
-{
-	twl4030_power_mmc_init(0);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-	static struct node_info nodes[] = {
-		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
-		{ "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
-	};
-
-	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-	return 0;
-}
-#endif
-
-void set_fdt(void)
-{
-	switch (gd->bd->bi_arch_number) {
-	case MACH_TYPE_IGEP0020:
-		setenv("fdtfile", "omap3-igep0020.dtb");
-		break;
-	case MACH_TYPE_IGEP0030:
-		setenv("fdtfile", "omap3-igep0030.dtb");
-		break;
-	}
-}
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
-	twl4030_power_init();
-
-	setup_net_chip();
-
-	omap_die_id_display();
-
-	set_fdt();
-
-	return 0;
-}
-
-void board_mtdparts_default(const char **mtdids, const char **mtdparts)
-{
-	struct mtd_info *mtd = get_mtd_device(NULL, 0);
-	if (mtd) {
-		static char ids[24];
-		static char parts[48];
-		const char *linux_name = "omap2-nand";
-		if (strncmp(mtd->name, "onenand0", 8) == 0)
-			linux_name = "omap2-onenand";
-		snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name);
-		snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)",
-		         linux_name, 4 * mtd->erasesize >> 10);
-		*mtdids = ids;
-		*mtdparts = parts;
-	}
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- *		hardware. Many pins need to be moved from protect to primary
- *		mode.
- */
-void set_muxconf_regs(void)
-{
-	MUX_DEFAULT();
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
-	MUX_IGEP0020();
-#endif
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-	MUX_IGEP0030();
-#endif
-}
diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
deleted file mode 100644
index 5698efa..0000000
--- a/board/isee/igep00x0/igep00x0.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _IGEP00X0_H_
-#define _IGEP00X0_H_
-
-/*
- * IEN  - Input Enable
- * IDIS - Input Disable
- * PTD  - Pull type Down
- * PTU  - Pull type Up
- * DIS  - Pull type selection is inactive
- * EN   - Pull type selection is active
- * M0   - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-#define MUX_DEFAULT()\
-	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
-	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
-	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
-	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
-	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
-	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
-	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
-	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
-	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
-	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
-	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
-	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
-	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
-	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
-	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
-	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
-	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
-	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
-	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
-	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
-	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
-	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
-	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
-	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
-	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
-	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
-	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
-	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
-	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
-	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
-	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
-	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
-	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
-	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
-	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
-	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
-	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
-	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
-	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
-	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
-	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
-	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
-	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
-	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
-	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
-	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
-	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
-	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
-	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
-	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
-	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
-	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
-	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
-	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
-	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
-	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
-	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
-	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
-	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
-	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
-	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
-	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
-	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
-	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
-	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
-	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
-	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
-	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
-	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
-	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
-	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
-	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
-	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
-	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
-	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
-	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
-	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
-	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
-	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
-	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
-	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
-	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
-	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
-	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
-	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
-	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
-	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
-	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
-	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
-	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
-	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
-	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
-	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
-	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
-	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
-	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
-	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
-	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
-	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
-	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
-	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
-#endif
-
-#define MUX_IGEP0020() \
-	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
-
-#define MUX_IGEP0030() \
-	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
-	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */
diff --git a/cmd/mem.c b/cmd/mem.c
index 83d34fa..58befe5 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -1210,7 +1210,6 @@ static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		ac--;
 	}
 #endif
-
 	return hash_command("crc32", flags, cmdtp, flag, ac, av);
 }
 
diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig
deleted file mode 100644
index a1991de..0000000
--- a/configs/am335x_igep0033_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_AM33XX=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_TARGET_AM335X_IGEP0033=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
deleted file mode 100644
index d3a84ce..0000000
--- a/configs/igep0020_defconfig
+++ /dev/null
@@ -1,50 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=27
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
deleted file mode 100644
index cb64d6f..0000000
--- a/configs/igep0030_defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_UBI=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=16
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep0032_defconfig b/configs/igep0032_defconfig
deleted file mode 100644
index 7e3e542..0000000
--- a/configs/igep0032_defconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP34XX=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_UBI=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep0046_imx6dl_2G_spl_defconfig b/configs/igep0046_imx6dl_2G_spl_defconfig
index de9cb94..3920647 100644
--- a/configs/igep0046_imx6dl_2G_spl_defconfig
+++ b/configs/igep0046_imx6dl_2G_spl_defconfig
@@ -34,3 +34,4 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6DL"
 CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_CMD_SAVEENV=n
\ No newline at end of file
diff --git a/include/configs/igep0046.h b/include/configs/igep0046.h
index 21b68df..efb0e19 100644
--- a/include/configs/igep0046.h
+++ b/include/configs/igep0046.h
@@ -31,6 +31,9 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
 #endif
 
+
+/* STAGES */
+#define CONFIG_LAST_STAGE_INIT
 /* CPU */
 #define CONFIG_IMX_THERMAL
 
@@ -110,8 +113,15 @@
 #define CONFIG_FAT_WRITE
 
 /* EEPROM Configs */
-#define CONFIG_SYS_I2C_EEPROM_BUS	2
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_EEPROM_SIZE				(4 * 1024)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_CMD_EEPROM_LAYOUT
+#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
+#define CONFIG_SYS_I2C_EEPROM_BUS			2
+#define CONFIG_SYS_I2C_EEPROM_ADDR			0x50
 
 /* NET Configs */
 #define CONFIG_ENV_OVERWRITE		/* To allow write MAC into ethaddr variable */
@@ -305,8 +315,8 @@ else
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs fec.macaddr=${ethaddr} " \
-		VIDEO_ARGS "\0" \
 		"ip=dhcp nfsroot=${serverip}:${rootnfs},v3,tcp " \
+		VIDEO_ARGS "\0" \
 	"netboot=echo Booting from net ...; " \
 		VIDEO_ARGS_SCRIPT \
 		"run netargs; " \