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| author | Ye Li <ye.li@nxp.com> | 2017-04-14 13:44:48 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-14 14:03:21 +0800 |
| commit | 43bff39513ae89c476751caff427b9855af78f7e (patch) | |
| tree | bbd492e7e326e54ec4b9a8ee0bc97d23e1b63fcb | |
| parent | f2d1f95053632e6460610bb0f49b36492280174b (diff) | |
| download | u-boot-imx-imx_v2016.03_4.1.33_7ulp_beta.zip u-boot-imx-imx_v2016.03_4.1.33_7ulp_beta.tar.gz u-boot-imx-imx_v2016.03_4.1.33_7ulp_beta.tar.bz2 | |
MLK-14693 mx7ulp: Change PLL rate calculation to avoid div 0rel_imx_4.1.33_7ulp_betaimx_v2016.03_4.1.33_7ulp_beta
The new ROM patch will set DENOM and NUM of APLL and SPLL to 0 to
workaround PLL issue.
When DENOM is 0, the PLL rate calculation will divide 0 and raise a signal.
raise: Signal # 8 caught
To avoid such problem, we change our calculation.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f28cf489e1b3864bac6bae4944d8a73bab30ec32)
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/scg.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c index d6ece80..6f0bf48 100644 --- a/arch/arm/cpu/armv7/mx7ulp/scg.c +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c @@ -500,7 +500,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_A7_APLL: reg = readl(&scg1_regs->apllcsr); @@ -529,7 +532,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_USB: reg = readl(&scg1_regs->upllcsr); |