From 43bff39513ae89c476751caff427b9855af78f7e Mon Sep 17 00:00:00 2001 From: Ye Li Date: Fri, 14 Apr 2017 13:44:48 +0800 Subject: MLK-14693 mx7ulp: Change PLL rate calculation to avoid div 0 The new ROM patch will set DENOM and NUM of APLL and SPLL to 0 to workaround PLL issue. When DENOM is 0, the PLL rate calculation will divide 0 and raise a signal. raise: Signal # 8 caught To avoid such problem, we change our calculation. Signed-off-by: Ye Li (cherry picked from commit f28cf489e1b3864bac6bae4944d8a73bab30ec32) --- arch/arm/cpu/armv7/mx7ulp/scg.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c index d6ece80..6f0bf48 100644 --- a/arch/arm/cpu/armv7/mx7ulp/scg.c +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c @@ -500,7 +500,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_A7_APLL: reg = readl(&scg1_regs->apllcsr); @@ -529,7 +532,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_USB: reg = readl(&scg1_regs->upllcsr); -- cgit v1.1