blob: 9db73d3249d2eeb0f58a345f40627ba9f8f63a1e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
/*
* Configuation settings for the Renesas Technology RSK 7203
*
* Copyright (C) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __RSK7203_H
#define __RSK7203_H
#undef DEBUG
#define CONFIG_CPU_SH7203 1
#define CONFIG_RSK7203 1
#define CONFIG_CMD_SDRAM
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define RSK7203_SDRAM_BASE 0x0C000000
#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
#define CONFIG_SYS_TEXT_BASE 0x0C7C0000
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BARGSIZE 512
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT 64
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
/* Network interface */
#define CONFIG_SMC911X
#define CONFIG_SMC911X_16_BIT
#define CONFIG_SMC911X_BASE (0x24000000)
#endif /* __RSK7203_H */
|
