blob: 296d77ac7806c4191b3a2fe057474929a1258341 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
/*
* Copyright (C) 2014 Samsung Electronics
*
* Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_PEACH_PI_H
#define __CONFIG_PEACH_PI_H
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"kernel_addr_r=0x22000000\0" \
"fdt_addr_r=0x23000000\0" \
"ramdisk_addr_r=0x23300000\0" \
"scriptaddr=0x30000000\0" \
"pxefile_addr_r=0x31000000\0"
#include <configs/exynos5420-common.h>
#include <configs/exynos5-dt-common.h>
#include <configs/exynos5-common.h>
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_TEXT_BASE 0x23E00000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
/* select serial console configuration */
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
/* Display */
#ifdef CONFIG_LCD
#define CONFIG_EXYNOS_FB
#define CONFIG_EXYNOS_DP
#define LCD_BPP LCD_COLOR16
#endif
#define CONFIG_POWER_TPS65090_EC
/* DRAM Memory Banks */
#define CONFIG_NR_DRAM_BANKS 7
#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
#endif /* __CONFIG_PEACH_PI_H */
|