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/*
* Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX6Q SabreSD board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX6QSABRESD_CONFIG_H
#define __MX6QSABRESD_CONFIG_H
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#endif
#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONSOLE_DEV "ttymxc0"
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */
#if defined(CONFIG_MX6QP)
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#elif defined(CONFIG_MX6Q)
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#elif defined(CONFIG_MX6DL)
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#elif defined(CONFIG_MX6SOLO)
#define PHYS_SDRAM_SIZE (512u * 1024 * 1024)
#endif
#include "mx6sabre_common.h"
/* Falcon Mode */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */
#ifdef CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_CS 0
#endif
/*
* imx6 q/dl/solo pcie would be failed to work properly in kernel, if
* the pcie module is iniialized/enumerated both in uboot and linux
* kernel.
* rootcause:imx6 q/dl/solo pcie don't have the reset mechanism.
* it is only be RESET by the POR. So, the pcie module only be
* initialized/enumerated once in one POR.
* Set to use pcie in kernel defaultly, mask the pcie config here.
* Remove the mask freely, if the uboot pcie functions, rather than
* the kernel's, are required.
*/
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX
#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
#endif
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
#endif
/*#define CONFIG_SPLASH_SCREEN*/
/*#define CONFIG_MXC_EPDC*/
/*
* SPLASH SCREEN Configs
*/
#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
/*
* Framebuffer and LCD
*/
#define CONFIG_CMD_BMP
#undef LCD_TEST_PATTERN
/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
#define LCD_BPP LCD_MONOCHROME
/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
#define CONFIG_WAVEFORM_BUF_SIZE 0x200000
#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */
#endif /* __MX6QSABRESD_CONFIG_H */
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