1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Andy Fleming <afleming@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
* Some part is taken from tsec.c
*/
#include <common.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
#include <fsl_tgec.h>
#include <fm_eth.h>
/*
* Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
*/
static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum, u16 value)
{
u32 mdio_ctl;
u32 stat_val;
struct tgec_mdio_controller *regs = bus->priv;
if (dev_addr == MDIO_DEVAD_NONE)
return 0;
/* Wait till the bus is free */
stat_val = MDIO_STAT_CLKDIV(100);
out_be32(®s->mdio_stat, stat_val);
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(®s->mdio_ctl, mdio_ctl);
/* Set the register address */
out_be32(®s->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Write the value to the register */
out_be32(®s->mdio_data, MDIO_DATA(value));
/* Wait till the MDIO write is complete */
while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
;
return 0;
}
/*
* Reads from register regnum in the PHY for device dev, returning the value.
* Clears miimcom first. All PHY configuration has to be done through the
* TSEC1 MIIM regs
*/
static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum)
{
u32 mdio_ctl;
u32 stat_val;
struct tgec_mdio_controller *regs = bus->priv;
if (dev_addr == MDIO_DEVAD_NONE)
return 0xffff;
stat_val = MDIO_STAT_CLKDIV(100);
out_be32(®s->mdio_stat, stat_val);
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the Port and Device Addrs */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(®s->mdio_ctl, mdio_ctl);
/* Set the register address */
out_be32(®s->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Initiate the read */
mdio_ctl |= MDIO_CTL_READ;
out_be32(®s->mdio_ctl, mdio_ctl);
/* Wait till the MDIO write is complete */
while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
;
/* Return all Fs if nothing was there */
if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
return 0xffff;
return in_be32(®s->mdio_data) & 0xffff;
}
static int tgec_mdio_reset(struct mii_dev *bus)
{
return 0;
}
int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate FM TGEC MDIO bus\n");
return -1;
}
bus->read = tgec_mdio_read;
bus->write = tgec_mdio_write;
bus->reset = tgec_mdio_reset;
strcpy(bus->name, info->name);
bus->priv = info->regs;
return mdio_register(bus);
}
|
