1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
|
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mapmem.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <clk.h>
#include <dm/device.h>
#include "clk-uniphier.h"
static int uniphier_clk_enable(struct udevice *dev, int index)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
struct uniphier_clk_gate_data *gate = priv->socdata->gate;
unsigned int nr_gate = priv->socdata->nr_gate;
void __iomem *reg;
u32 mask, data, tmp;
int i;
for (i = 0; i < nr_gate; i++) {
if (gate[i].index != index)
continue;
reg = priv->base + gate[i].reg;
mask = gate[i].mask;
data = gate[i].data & mask;
tmp = readl(reg);
tmp &= ~mask;
tmp |= data & mask;
debug("%s: %p: %08x\n", __func__, reg, tmp);
writel(tmp, reg);
}
return 0;
}
static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
unsigned int nr_rdata = priv->socdata->nr_rate;
void __iomem *reg;
u32 mask, data;
ulong matched_rate = 0;
int i;
for (i = 0; i < nr_rdata; i++) {
if (rdata[i].index != index)
continue;
if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
return rdata[i].rate;
reg = priv->base + rdata[i].reg;
mask = rdata[i].mask;
data = rdata[i].data & mask;
if ((readl(reg) & mask) == data) {
if (matched_rate && rdata[i].rate != matched_rate) {
printf("failed to get clk rate for insane register values\n");
return -EINVAL;
}
matched_rate = rdata[i].rate;
}
}
debug("%s: rate = %lu\n", __func__, matched_rate);
return matched_rate;
}
static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
unsigned int nr_rdata = priv->socdata->nr_rate;
void __iomem *reg;
u32 mask, data, tmp;
ulong best_rate = 0;
int i;
/* first, decide the best match rate */
for (i = 0; i < nr_rdata; i++) {
if (rdata[i].index != index)
continue;
if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
return 0;
if (rdata[i].rate > best_rate && rdata[i].rate <= rate)
best_rate = rdata[i].rate;
}
if (!best_rate)
return -ENODEV;
debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
rate, best_rate);
/* second, really set registers */
for (i = 0; i < nr_rdata; i++) {
if (rdata[i].index != index || rdata[i].rate != best_rate)
continue;
reg = priv->base + rdata[i].reg;
mask = rdata[i].mask;
data = rdata[i].data & mask;
tmp = readl(reg);
tmp &= ~mask;
tmp |= data;
debug("%s: %p: %08x\n", __func__, reg, tmp);
writel(tmp, reg);
}
return best_rate;
}
const struct clk_ops uniphier_clk_ops = {
.enable = uniphier_clk_enable,
.get_periph_rate = uniphier_clk_get_rate,
.set_periph_rate = uniphier_clk_set_rate,
};
int uniphier_clk_probe(struct udevice *dev)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->base = map_sysmem(addr, SZ_4K);
if (!priv->base)
return -ENOMEM;
priv->socdata = (void *)dev_get_driver_data(dev);
return 0;
}
int uniphier_clk_remove(struct udevice *dev)
{
struct uniphier_clk_priv *priv = dev_get_priv(dev);
unmap_sysmem(priv->base);
return 0;
}
|
