1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
|
/*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <ppc4xx.h>
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
#include <asm/4xx_pcie.h>
DECLARE_GLOBAL_DATA_PTR;
void __ft_board_setup(void *blob, bd_t *bd)
{
int rc;
int i;
u32 bxcr;
u32 ranges[EBC_NUM_BANKS * 4];
u32 *p = ranges;
char *ebc_path = "/plb/opb/ebc";
ft_cpu_setup(blob, bd);
/*
* Read 4xx EBC bus bridge registers to get mappings of the
* peripheral banks into the OPB/PLB address space
*/
for (i = 0; i < EBC_NUM_BANKS; i++) {
mtdcr(ebccfga, EBC_BXCR(i));
bxcr = mfdcr(ebccfgd);
if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
*p++ = i;
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS_MASK;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
}
}
/* Some 405 PPC's have EBC as direct PLB child in the dts */
if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
strcpy(ebc_path, "/plb/ebc");
rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
(p - ranges) * sizeof(u32), 1);
if (rc) {
printf("Unable to update property EBC mappings, err=%s\n",
fdt_strerror(rc));
}
}
void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
/*
* Fixup all PCIe nodes by setting the device_type property
* to "pci-endpoint" instead is "pci" for endpoint ports.
* This property will get checked later by the Linux driver
* to properly configure the PCIe port in Linux (again).
*/
void fdt_pcie_setup(void *blob)
{
const char *compat = "ibm,plb-pciex";
const char *prop = "device_type";
const char *prop_val = "pci-endpoint";
const u32 *port;
int no;
int rc;
/* Search first PCIe node */
no = fdt_node_offset_by_compatible(blob, -1, compat);
while (no != -FDT_ERR_NOTFOUND) {
port = fdt_getprop(blob, no, "port", NULL);
if (port == NULL) {
printf("WARNING: could not find port property\n");
} else {
if (is_end_point(*port)) {
rc = fdt_setprop(blob, no, prop, prop_val,
strlen(prop_val) + 1);
if (rc < 0)
printf("WARNING: could not set %s for %s: %s.\n",
prop, compat, fdt_strerror(rc));
}
}
/* Jump to next PCIe node */
no = fdt_node_offset_by_compatible(blob, no, compat);
}
}
void ft_cpu_setup(void *blob, bd_t *bd)
{
sys_info_t sys_info;
get_sys_info(&sys_info);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
bd->bi_intfreq, 1);
do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
sys_info.freqEBC, 1);
else
do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
sys_info.freqEBC, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
/*
* Setup all baudrates for the UARTs
*/
do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1);
/*
* Fixup all ethernet nodes
* Note: aliases in the dts are required for this
*/
fdt_fixup_ethernet(blob);
/*
* Fixup all available PCIe nodes by setting the device_type property
*/
fdt_pcie_setup(blob);
}
#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
|
