1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
|
/*
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This provides a bit-banged interface to the ethernet MII management
* channel.
*/
#include <common.h>
#include <ioports.h>
#include <ppc_asm.tmpl>
#ifdef CONFIG_BITBANGMII
/*****************************************************************************
*
* Utility to send the preamble, address, and register (common to read
* and write).
*/
static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
int j; /* counter */
#ifndef CONFIG_EP8248
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
* The IEEE spec says this is a PHY optional requirement. The AMD
* 79C874 requires one after power up and one after a MII communications
* error. This means that we are doing more preambles than we need,
* but it is safer and will be much more robust.
*/
MDIO_ACTIVE;
MDIO (1);
for (j = 0; j < 32; j++) {
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
}
/* send the start bit (01) and the read opcode (10) or write (10) */
MDC (0);
MDIO (0);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (1);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (read);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (!read);
MIIDELAY;
MDC (1);
MIIDELAY;
/* send the PHY address */
for (j = 0; j < 5; j++) {
MDC (0);
if ((addr & 0x10) == 0) {
MDIO (0);
} else {
MDIO (1);
}
MIIDELAY;
MDC (1);
MIIDELAY;
addr <<= 1;
}
/* send the register address */
for (j = 0; j < 5; j++) {
MDC (0);
if ((reg & 0x10) == 0) {
MDIO (0);
} else {
MDIO (1);
}
MIIDELAY;
MDC (1);
MIIDELAY;
reg <<= 1;
}
}
/*****************************************************************************
*
* Read a MII PHY register.
*
* Returns:
* 0 on success
*/
int bb_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
int j; /* counter */
#ifndef CONFIG_EP8248
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
miiphy_pre (1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
MDC (0);
MDIO_TRISTATE;
MIIDELAY;
MDC (1);
MIIDELAY;
/* check the turnaround bit: the PHY should be driving it to zero */
if (MDIO_READ != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
}
return (-1);
}
MDC (0);
MIIDELAY;
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
MDC (1);
MIIDELAY;
rdreg <<= 1;
rdreg |= MDIO_READ;
MDC (0);
MIIDELAY;
}
MDC (1);
MIIDELAY;
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
*value = rdreg;
#ifdef DEBUG
printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
#endif
return 0;
}
/*****************************************************************************
*
* Write a MII PHY register.
*
* Returns:
* 0 on success
*/
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
int j; /* counter */
#ifndef CONFIG_EP8248
volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
#endif
miiphy_pre (0, addr, reg);
/* send the turnaround (10) */
MDC (0);
MDIO (1);
MIIDELAY;
MDC (1);
MIIDELAY;
MDC (0);
MDIO (0);
MIIDELAY;
MDC (1);
MIIDELAY;
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
MDC (0);
if ((value & 0x00008000) == 0) {
MDIO (0);
} else {
MDIO (1);
}
MIIDELAY;
MDC (1);
MIIDELAY;
value <<= 1;
}
/*
* Tri-state the MDIO line.
*/
MDIO_TRISTATE;
MDC (0);
MIIDELAY;
MDC (1);
MIIDELAY;
return 0;
}
#endif /* CONFIG_BITBANGMII */
|
