1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
|
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
*
* (C) Copyright 2008
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <pci.h>
#include <spi.h>
#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include "mvblm7.h"
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
msize = CFG_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
LAWAR_SIZE);
im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CFG_DDR_MODE;
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
udelay(300);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return CFG_DDR_SIZE;
}
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CFG_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
/* return total bus RAM size(bytes) */
return msize * 1024 * 1024;
}
int checkboard(void)
{
puts("Board: Matrix Vision mvBlueLYNX-M7 " MV_VERSION "\n");
return 0;
}
u8 *dhcp_vendorex_prep(u8 *e)
{
char *ptr;
/* DHCP vendor-class-identifier = 60 */
ptr = getenv("dhcp_vendor-class-identifier");
if (ptr) {
*e++ = 60;
*e++ = strlen(ptr);
while (*ptr)
*e++ = *ptr++;
}
/* DHCP_CLIENT_IDENTIFIER = 61 */
ptr = getenv("dhcp_client_id");
if (ptr) {
*e++ = 61;
*e++ = strlen(ptr);
while (*ptr)
*e++ = *ptr++;
}
return e;
}
u8 *dhcp_vendorex_proc(u8 *popt)
{
return NULL;
}
#ifdef CONFIG_HARD_SPI
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
iopd->dat &= ~MVBLM7_MMC_CS;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
iopd->dat |= ~MVBLM7_MMC_CS;
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
|
