path: root/board/isee/igep0146/igep0146.c

/*
 * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
 *
 * Source file for IGEP0146 board
 *
 * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/mx6-ddr.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <malloc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx6/sys_proto.h>
#include <asm/io.h>
#include "../common/igep_common.h"

#include <mmc.h>
#include <fsl_esdhc.h>

/*
#include <usb.h>
#include <usb/ehci-ci.h>
*/

#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include "igep0146_eeprom.h"

DECLARE_GLOBAL_DATA_PTR;

/* MACRO MUX defines */

#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define GPIO_LED_PAD_CTRL  (PAD_CTL_PUS_22K_UP |	\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_SRE_FAST )

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_SPEED_HIGH   |                                   \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define ENET_TX_CTRL  ( PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | PAD_CTL_SPEED_HIGH  | \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)

#define ENET_RX_CTRL  ( PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | PAD_CTL_SPEED_HIGH  | \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_HYS)

#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |	\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS |	\
	PAD_CTL_PUE | PAD_CTL_PKE)

#define USDHC_PAD_CLK_CTRL (PAD_CTL_PUS_100K_DOWN |	\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm |	\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#ifdef CONFIG_SYS_I2C_MXC
#define I2C_PAD_CTRL  ( PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | PAD_CTL_SPEED_MED |	\
	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
#endif

/* Audio reset */
#define AUDIO_RESET	IMX_GPIO_NR(4, 17)
/* Ethernet Phy 1 reset */
#define ETH_PHY_RESET	IMX_GPIO_NR(1, 10)
/* eMMC reset */
#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 10)

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
	gd->bd->bi_dram[0].size = imx_ddr_size();
}

/* uart */
static iomux_v3_cfg_t const uart3_pads[] =
{
	MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const led_pads[] = {
	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
	/* Warning This GPIO actually controls if we select SD or WiFi through a MUX */
	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),

};

#ifdef CONFIG_FEC_MXC
/* ethernet */
static iomux_v3_cfg_t const enet1_pads[] = {
	
	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),

	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
	
	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_TX_CTRL),
	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_TX_CTRL),

	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_RX_CTRL),
	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_RX_CTRL),

	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),

	/* ethernet reset */
	MX6_PAD_JTAG_MOD__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),

};
#endif

/* sd 1 */
static iomux_v3_cfg_t const usdhc1_pads[] = {
	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

};

/* emmc */
static iomux_v3_cfg_t const usdhc2_pads[] = {
	
	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

	/* emmc Reset */
	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

/* gpio misc */
static iomux_v3_cfg_t const init_pads[] =
{
	/* TLV320AIC3106 Audio codec Reset*/
	MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

const uchar igep_mac0 [6] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0xff };
//const uchar igep_mac0 [6] = { 0xb0, 0xd5, 0xcc, 0xb2, 0xa5, 0xb9 };

static int igep_eeprom_valid = 0;
static struct igep_mf_setup igep0046_eeprom_config;

/* i2c */
#ifdef CONFIG_SYS_I2C_MXC
static struct i2c_pads_info i2c_pad_info1 =
{
	.scl =
	{
		.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 28)
	},
	.sda =
	{
		.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 29)
	}
};

static struct i2c_pads_info i2c_pad_info2 =
{
	.scl =
	{
		.i2c_mode = MX6_PAD_UART5_TX_DATA__I2C2_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_UART5_TX_DATA__GPIO1_IO30 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 30)
	},
	.sda =
	{
		.i2c_mode = MX6_PAD_UART5_RX_DATA__I2C2_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_UART5_RX_DATA__GPIO1_IO31 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 31)
	}
};
#endif


static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}

static void setup_iomux_leds(void)
{
	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
}

/*
static void setup_iomux_usdhc(void)
{
	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));

}
*/

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet1_pads, ARRAY_SIZE(enet1_pads));
}

static void setup_iomux_misc(void)
{
	imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
}


const uchar* get_mac_address (void)
{
	if(igep_eeprom_valid)
		return igep0046_eeprom_config.bmac0;
	return igep_mac0;
}

#ifdef CONFIG_BASE0040
static void reset_audio(void)
{
	/* Audio Reset */
	gpio_direction_output(AUDIO_RESET, 0);
	mdelay(5);
}
#endif

#ifdef CONFIG_FEC_MXC

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
}
#endif /* CONFIG_RESET_PHY_R */

void mu_reset_phy(void)
{
	/* Reset LAN8720 PHY */
	gpio_request(ETH_PHY_RESET, "LAN8720 PHY RST");
	gpio_direction_output(ETH_PHY_RESET , 0);
	mdelay(10);
	gpio_set_value(ETH_PHY_RESET, 1);
	mdelay(10);
}

static int setup_phy(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int ret;
	int fec_id = 0;
	
	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
	if (ret)
		return ret;

	enable_enet_clk(1);
	return 0;

}

int board_eth_init(bd_t *bis)
{

	int ret = 0 ;
	eth_setenv_enetaddr("ethaddr", get_mac_address());
	setup_iomux_enet();
	mu_reset_phy();

	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
	if (ret)
		printf("FEC%d MXC: %s:failed\n", 0, __func__);

	return 0;
}

#endif

static struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC1_BASE_ADDR, 0, 4},
	{USDHC2_BASE_ADDR, 0, 8},
};

int board_mmc_getcd(struct mmc *mmc)
{

	/* we will consider at the moment that SD1 / eMMC are always present */
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		/* SD case */
		ret = 1;
		/* WiFi case */
		break;
	case USDHC2_BASE_ADDR:
		/* eMMC case */
		/* Nand case */
		/* QPSI case */
		/* SD2 case */
		ret = 1;
		break;
	}

	return ret;

}
int board_mmc_init(bd_t *bis)
{
	int i, ret;

	/*
	 * According to the board_mmc_init() the following map is done:
	 * (U-boot device node)    (Physical Port)
	 * mmc0                    USDHC1	--> SD1 / Wifi
	 * mmc1                    USDHC2	--> eMMC / NAND / QSPI / SD2
	 */
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 			/* USDHC1 Clock */
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 			/* USDHC2 Clock */
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
			break;
		}	
		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize mmc dev %d\n", i);
		}
	}
	return 0;
}



int checkboard(void)
{
	return 0;
}

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_leds();
	setup_iomux_misc();
	return 0;
}

int board_init(void)
{

	u32 crc_value = 0;
   	u32 crc_save_value = 0;

#ifdef CONFIG_BASE0040
	reset_audio();
#endif

#ifdef CONFIG_SYS_I2C_MXC
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	mdelay(1);
#endif

  if(check_eeprom() != 0){
	printf("EEPROM: not found\n");
    }else{
		/* Read configuration from eeprom */
		if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup)))
	  	printf("EEPROM: read fail\n");	
		/* Verify crc32 */
	   	crc_save_value = igep0046_eeprom_config.crc32;
    	igep0046_eeprom_config.crc32 = 0;
	   	crc_value = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
		if(crc_save_value != crc_value){
       	printf("EEPROM: CRC32 failed. Loading default MAC\n");				
		}else{
	    printf("EEPROM: CRC32 OK! Loading MAC from eeprom\n");	       		
	  	igep_eeprom_valid = 1;
		}
	}

#ifdef	CONFIG_FEC_MXC
	setup_phy();
#endif

	return 0;	
}


int board_late_init(void)
{	
	checkboard();
	return 0;
}

#ifdef CONFIG_LDO_BYPASS_CHECK
/* TODO, use external pmic, for now always ldo_enable */
void ldo_mode_set(int ldo_bypass)
{
	return;
}
#endif

/* Configure for SPL BUILD */

#ifdef CONFIG_SPL_BUILD
#include <libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>

/* ENTIRE RAM CALIBRATION STRUCTURES MISSING */

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0xFFFFFFFF, &ccm->CCGR0);
	writel(0xFFFFFFFF, &ccm->CCGR1);
	writel(0xFFFFFFFF, &ccm->CCGR2);
	writel(0xFFFFFFFF, &ccm->CCGR3);
	writel(0xFFFFFFFF, &ccm->CCGR4);
	writel(0xFFFFFFFF, &ccm->CCGR5);
	writel(0xFFFFFFFF, &ccm->CCGR6);
	writel(0xFFFFFFFF, &ccm->CCGR7);
}

static void spl_dram_init(void)
{
	/* COMMENTED UNTIL VALID RAM CONFIGURATION FOUND */ 
	/*
	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
	*/
}

/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* its our chance to print info about boot device */
void spl_board_init(void)
{
	
}

void board_init_f(ulong dummy)
{
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	/* iomux of uart and leds */
	board_early_init_f();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();
	
	/* DDR initialization */
	spl_dram_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	/* load/boot image from boot device */
	board_init_r(NULL, 0);
}
#endif