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/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mx7ulp-pins.h>
#include <asm/arch/iomux.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE)
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
static iomux_cfg_t const lpuart4_pads[] = {
MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
ARRAY_SIZE(lpuart4_pads));
}
#ifdef CONFIG_FSL_QSPI
#ifndef CONFIG_DM_SPI
static iomux_cfg_t const quadspi_pads[] = {
MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
};
#endif
int board_qspi_init(void)
{
u32 val;
#ifndef CONFIG_DM_SPI
mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
#endif
/* enable clock */
val = readl(PCC1_RBASE + 0x94);
if (!(val & 0x20000000)) {
writel(0x03000003, (PCC1_RBASE + 0x94));
writel(0x43000003, (PCC1_RBASE + 0x94));
}
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_FSL_QSPI
board_qspi_init();
#endif
return 0;
}
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