1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
|
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
/* DDR script */
.macro imx7d_19x19_lpddr3_arm2_setting
/* Configure ocram_epdc */
ldr r0, =IOMUXC_GPR_BASE_ADDR
ldr r1, =0x4f400005
str r1, [r0, #0x4]
ldr r0, =SRC_BASE_ADDR
ldr r1, =0x2
ldr r2, =0x1000
str r1, [r0, r2]
ldr r0, =DDRC_IPS_BASE_ADDR
ldr r1, =0x03040008
str r1, [r0]
ldr r1, =0x00200038
str r1, [r0, #0x64]
ldr r1, =0x1
str r1, [r0, #0x490]
ldr r1, =0x00350001
str r1, [r0, #0xd0]
ldr r1, =0x00c3000a
str r1, [r0, #0xdc]
ldr r1, =0x00010000
str r1, [r0, #0xe0]
ldr r1, =0x00110006
str r1, [r0, #0xe4]
ldr r1, =0x33f
str r1, [r0, #0xf4]
ldr r1, =0x0a0e110b
str r1, [r0, #0x100]
ldr r1, =0x00020211
str r1, [r0, #0x104]
ldr r1, =0x03060708
str r1, [r0, #0x108]
ldr r1, =0x00a0500c
str r1, [r0, #0x10c]
ldr r1, =0x05020307
str r1, [r0, #0x110]
ldr r1, =0x02020404
str r1, [r0, #0x114]
ldr r1, =0x02020003
str r1, [r0, #0x118]
ldr r1, =0x00000202
str r1, [r0, #0x11c]
ldr r1, =0x00000202
str r1, [r0, #0x120]
ldr r1, =0x00600018
str r1, [r0, #0x180]
ldr r1, =0x00e00100
str r1, [r0, #0x184]
ldr r1, =0x02098205
str r1, [r0, #0x190]
ldr r1, =0x00060303
str r1, [r0, #0x194]
ldr r1, =0x80400003
str r1, [r0, #0x1a0]
ldr r1, =0x00100020
str r1, [r0, #0x1a4]
ldr r1, =0x80100004
str r1, [r0, #0x1a8]
ldr r1, =0x00000016
str r1, [r0, #0x200]
ldr r1, =0x00171717
str r1, [r0, #0x204]
ldr r1, =0x00000f00
str r1, [r0, #0x210]
ldr r1, =0x05050505
str r1, [r0, #0x214]
ldr r1, =0x0f0f0505
str r1, [r0, #0x218]
ldr r1, =0x06000601
str r1, [r0, #0x240]
mov r1, #0x0
str r1, [r0, #0x244]
ldr r0, =SRC_BASE_ADDR
mov r1, #0x0
ldr r2, =0x1000
str r1, [r0, r2]
ldr r0, =DDRPHY_IPS_BASE_ADDR
ldr r1, =0x17421e40
str r1, [r0]
ldr r1, =0x10210100
str r1, [r0, #0x4]
ldr r1, =0x00010000
str r1, [r0, #0x8]
ldr r1, =0x0007080c
str r1, [r0, #0x10]
ldr r1, =0x1010007e
str r1, [r0, #0xb0]
ldr r1, =0x01010000
str r1, [r0, #0x1c]
ldr r1, =0x0db60d6e
str r1, [r0, #0x9c]
ldr r1, =0x06060606
str r1, [r0, #0x30]
ldr r1, =0x0a0a0a0a
str r1, [r0, #0x20]
ldr r1, =0x01000008
str r1, [r0, #0x50]
ldr r1, =0x00000008
str r1, [r0, #0x50]
ldr r1, =0x0000000f
str r1, [r0, #0x18]
ldr r1, =0x1e487304
str r1, [r0, #0xc0]
ldr r1, =0x1e487304
str r1, [r0, #0xc0]
ldr r1, =0x1e487306
str r1, [r0, #0xc0]
ldr r1, =0x1e4c7304
str r1, [r0, #0xc0]
wait_zq:
ldr r1, [r0, #0xc4]
tst r1, #0x1
beq wait_zq
ldr r1, =0x1e487304
str r1, [r0, #0xc0]
ldr r0, =CCM_BASE_ADDR
mov r1, #0x0
ldr r2, =0x4130
str r1, [r0, r2]
ldr r0, =IOMUXC_GPR_BASE_ADDR
mov r1, #0x178
str r1, [r0, #0x20]
ldr r0, =CCM_BASE_ADDR
mov r1, #0x2
ldr r2, =0x4130
str r1, [r0, r2]
ldr r0, =DDRC_IPS_BASE_ADDR
wait_stat:
ldr r1, [r0, #0x4]
tst r1, #0x1
beq wait_stat
.endm
.macro imx7d_19x19_lpddr2_arm2_setting
/* Configure ocram_epdc */
ldr r0, =IOMUXC_GPR_BASE_ADDR
ldr r1, =0x4f400005
str r1, [r0, #0x4]
ldr r0, =SRC_BASE_ADDR
ldr r1, =0x2
ldr r2, =0x1000
str r1, [r0, r2]
ldr r0, =DDRC_IPS_BASE_ADDR
ldr r1, =0x03020004
str r1, [r0]
ldr r1, =0x80400003
str r1, [r0, #0x1a0]
ldr r1, =0x00100020
str r1, [r0, #0x1a4]
ldr r1, =0x80100004
str r1, [r0, #0x1a8]
ldr r1, =0x00200023
str r1, [r0, #0x64]
ldr r1, =0x1
str r1, [r0, #0x490]
ldr r1, =0x00350001
str r1, [r0, #0xd0]
ldr r1, =0x00001105
str r1, [r0, #0xd8]
ldr r1, =0x00c20006
str r1, [r0, #0xdc]
ldr r1, =0x00020000
str r1, [r0, #0xe0]
ldr r1, =0x00110006
str r1, [r0, #0xe4]
ldr r1, =0x33f
str r1, [r0, #0xf4]
ldr r1, =0x080e110b
str r1, [r0, #0x100]
ldr r1, =0x00020211
str r1, [r0, #0x104]
ldr r1, =0x02040706
str r1, [r0, #0x108]
ldr r1, =0x00504000
str r1, [r0, #0x10c]
ldr r1, =0x05010307
str r1, [r0, #0x110]
ldr r1, =0x02020404
str r1, [r0, #0x114]
ldr r1, =0x02020003
str r1, [r0, #0x118]
ldr r1, =0x00000202
str r1, [r0, #0x11c]
ldr r1, =0x00000202
str r1, [r0, #0x120]
ldr r1, =0x00600018
str r1, [r0, #0x180]
ldr r1, =0x00e00100
str r1, [r0, #0x184]
ldr r1, =0x02098203
str r1, [r0, #0x190]
ldr r1, =0x00060303
str r1, [r0, #0x194]
ldr r1, =0x00000015
str r1, [r0, #0x200]
ldr r1, =0x00161616
str r1, [r0, #0x204]
ldr r1, =0x00000f0f
str r1, [r0, #0x210]
ldr r1, =0x04040404
str r1, [r0, #0x214]
ldr r1, =0x0f0f0404
str r1, [r0, #0x218]
ldr r1, =0x06000600
str r1, [r0, #0x240]
mov r1, #0x0
str r1, [r0, #0x244]
ldr r0, =SRC_BASE_ADDR
mov r1, #0x0
ldr r2, =0x1000
str r1, [r0, r2]
ldr r0, =DDRPHY_IPS_BASE_ADDR
ldr r1, =0x17421640
str r1, [r0]
ldr r1, =0x10210100
str r1, [r0, #0x4]
ldr r1, =0x00010000
str r1, [r0, #0x8]
ldr r1, =0x00050408
str r1, [r0, #0x10]
ldr r1, =0x1010007e
str r1, [r0, #0xb0]
ldr r1, =0x01010000
str r1, [r0, #0x1c]
ldr r1, =0x00000d6e
str r1, [r0, #0x9c]
ldr r1, =0x0000000f
str r1, [r0, #0x18]
ldr r1, =0x06060606
str r1, [r0, #0x30]
ldr r1, =0x0a0a0a0a
str r1, [r0, #0x20]
ldr r1, =0x01000008
str r1, [r0, #0x50]
ldr r1, =0x00000008
str r1, [r0, #0x50]
ldr r1, =0x0e487304
str r1, [r0, #0xc0]
ldr r1, =0x0e4c7304
str r1, [r0, #0xc0]
ldr r1, =0x0e4c7306
str r1, [r0, #0xc0]
wait_zq:
ldr r1, [r0, #0xc4]
tst r1, #0x1
beq wait_zq
ldr r1, =0x0e4c7304
str r1, [r0, #0xc0]
ldr r1, =0x0e487304
str r1, [r0, #0xc0]
ldr r0, =CCM_BASE_ADDR
mov r1, #0x0
ldr r2, =0x4130
str r1, [r0, r2]
ldr r0, =IOMUXC_GPR_BASE_ADDR
mov r1, #0x1f8
str r1, [r0, #0x20]
ldr r0, =CCM_BASE_ADDR
mov r1, #0x2
ldr r2, =0x4130
str r1, [r0, r2]
ldr r0, =DDRC_IPS_BASE_ADDR
wait_stat:
ldr r1, [r0, #0x4]
tst r1, #0x1
beq wait_stat
.endm
.macro imx7_clock_gating
.endm
.macro imx7_qos_setting
.endm
.macro imx7_ddr_setting
#if defined (CONFIG_MX7D_LPDDR2)
imx7d_19x19_lpddr2_arm2_setting
#else
imx7d_19x19_lpddr3_arm2_setting
#endif
.endm
/* include the common plugin code here */
#include <asm/arch/mx7_plugin.S>
|