1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
|
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/mx51.h>
#include "board-imx51.h"
/*
* return soc version
* 0x10: TO1
* 0x20: TO2
* 0x30: TO3
*/
.macro check_soc_version ret, tmp
.endm
/*
* L2CC Cache setup/invalidation/disable
*/
.macro init_l2cc
/* reconfigure L2 cache aux control reg */
ldr r0, =0x03C000C4
mcr p15, 1, r0, c9, c0, 2
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.*/
.macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =AIPS1_BASE_ADDR
ldr r1, =0x77777777
str r1, [r0, #0x0]
str r1, [r0, #0x4]
ldr r0, =AIPS2_BASE_ADDR
str r1, [r0, #0x0]
str r1, [r0, #0x4]
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
.endm /* init_aips */
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
.macro init_max
.endm /* init_max */
/* M4IF setup */
.macro init_m4if
/* VPU and IPU given higher priority (0x4)
* IPU accesses with ID=0x1 given highest priority (=0xA)
*/
ldr r0, =M4IF_BASE_ADDR
ldr r1, =0x00000203
str r1, [r0, #0x40]
ldr r1, =0x0
str r1, [r0, #0x44]
ldr r1, =0x00120125
str r1, [r0, #0x9C]
ldr r1, =0x001901A3
str r1, [r0, #0x48]
/*
ldr r1, =0x00000a01
str r1, [r0, #0x48]
ldr r1, =0x00000404
str r1, [r0, #0x40]
*/
.endm /* init_m4if */
/* To support 133MHz DDR */
.macro init_drive_strength
.endm /* init_drive_strength */
/* CPLD on CS5 setup */
.macro init_debug_board
.endm /* init_debug_board */
.macro setup_pll pll, freq
ldr r2, =\pll
ldr r1, =0x00001232
str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r3, [r2, #PLL_DP_OP]
str r3, [r2, #PLL_DP_HFS_OP]
str r4, [r2, #PLL_DP_MFD]
str r4, [r2, #PLL_DP_HFS_MFD]
str r5, [r2, #PLL_DP_MFN]
str r5, [r2, #PLL_DP_HFS_MFN]
ldr r1, =0x00001232
str r1, [r2, #PLL_DP_CTL]
1: ldr r1, [r2, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
.macro init_clock
ldr r0, =CCM_BASE_ADDR
mov r1, #0x00060000
str r1, [r0, #CLKCTL_CCDR]
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
mov r3, #DP_OP_800
mov r4, #DP_MFD_800
mov r5, #DP_MFN_800
setup_pll PLL1_BASE_ADDR
mov r3, #DP_OP_665
mov r4, #DP_MFD_665
mov r5, #DP_MFN_665
setup_pll PLL3_BASE_ADDR
/* Switch peripheral to PLL 3 */
ldr r1, =0x0000D3C0
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x033B9145
str r1, [r0, #CLKCTL_CBCDR]
mov r3, #DP_OP_665
mov r4, #DP_MFD_665
mov r5, #DP_MFN_665
setup_pll PLL2_BASE_ADDR
/* Switch peripheral to PLL2 */
ldr r1, =0x013B9145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x0000E3C0
str r1, [r0, #CLKCTL_CBCMR]
mov r3, #DP_OP_216
mov r4, #DP_MFD_216
mov r5, #DP_MFN_216
setup_pll PLL3_BASE_ADDR
/* Set the platform clock dividers */
ldr r2, =ARM_BASE_ADDR
ldr r1, =0x00000725
str r1, [r2, #0x14]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #CLKCTL_CCSR]
str r1, [r0, #CLKCTL_CACRR]
/* Use lp_apm (24MHz) source for perclk */
mov r2, #0x48
ldr r2, [r0]
cmp r2, #0x10
ldrhs r1, =0x000020C2
ldrlo r1, =0x0000E3C2
str r1, [r0, #CLKCTL_CBCMR]
/* TO1.x emi = ahb, all perclk dividers are 1 since using 24MHz */
/* TO2.x ddr from PLL1, all perclk dividers are 1 since using 24MHz */
ldrhs r1, =0x59239100
ldrlo r1, =0x013D9100
strlo r1, [r0, #CLKCTL_CBCDR]
/* use PLL2 for UART source, get 66.5MHz */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0
bne 1b
mov r1, #0x0
str r1, [r0, #CLKCTL_CCDR]
.endm
.macro setup_wdog
ldr r0, =WDOG1_BASE_ADDR
mov r1, #0x30
strh r1, [r0]
.endm
.section ".text.init", "x"
.globl lowlevel_init
lowlevel_init:
/* Platform CHIP level init*/
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #(1 << 23)
str r1, [r0, #0x0]
ldr r1, [r0, #0x4]
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
#ifdef TURN_OFF_IMPRECISE_ABORT
mrs r0, cpsr
bic r0, r0, #0x100
msr cpsr, r0
#endif
mrc 15, 0, r1, c1, c0, 0
#ifndef BRANCH_PREDICTION_ENABLE
mrc 15, 0, r0, c1, c0, 1
bic r0, r0, #7
mcr 15, 0, r0, c1, c0, 1
#else
mrc 15, 0, r0, c1, c0, 1
orr r0, r0, #7
mcr 15, 0, r0, c1, c0, 1
orr r1, r1, #(1<<11)
#endif
#ifdef UNALIGNED_ACCESS_ENABLE
orr r1, r1, #(1<<22)
#endif
#ifdef LOW_INT_LATENCY_ENABLE
orr r1, r1, #(1<<21)
#endif
mcr 15, 0, r1, c1, c0, 0
mov r0, #0
#ifdef BRANCH_PREDICTION_ENABLE
mcr 15, 0, r0, c15, c2, 4
#endif
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
init_l2cc
init_aips
init_max
init_m4if
init_drive_strength
cmp pc, #PHYS_SDRAM_1
blo init_clock_start
cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
blo init_clock_start
init_clock_start:
init_clock
init_debug_board
/*init_sdram*/
/* return from mxc_nand_load */
/* r12 saved upper lr*/
b mxc_nand_load
/* Board level setting value */
DDR_PERCHARGE_CMD: .word 0x04008008
DDR_REFRESH_CMD: .word 0x00008010
DDR_LMR1_W: .word 0x00338018
DDR_LMR_CMD: .word 0xB2220000
DDR_TIMING_W: .word 0xB02567A9
DDR_MISC_W: .word 0x000A0104
|
