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/*
* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* sd, nand
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#define __ASSEMBLY__
#include <config.h>
/* Enable all clocks */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff
/* ddr io type */
DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
/* clock */
DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
/* control and address */
DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
configured using Group Control Register:
IOMUXC_SW_PAD_CTL_GRP_CTLDS */
DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
/* data strobes */
DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
/* data */
DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
/*
* DDR Controller Registers
*
* Manufacturer: IM
* Device Part Number: IME1G16D3EEBG-15EI
* Clock Freq.: 400MHz
* Density per CS in Gb: 1
* Chip Selects used: 1
* Number of Banks: 8
* Row address: 13
* Column address: 10
* Data bus width 16
*/
DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
during MMDC set up */
/*
* Calibration setup
*/
DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
periodic HW ZQ calibration. */
/*
* For target board, may need to run write leveling calibration to fine tune
* these settings.
*/
DATA 4 0x021b080c 0x00000000
/* Read DQS Gating calibration */
DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
/* Read calibration */
DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
/* Write calibration */
DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
/*
* read data bit delay: (3 is the reccommended default value, although out of
* reset value is 0)
*/
DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
DATA 4 0x021b082c 0xF3333333
DATA 4 0x021b0830 0xF3333333
DATA 4 0x021b08c0 0x00921012
/* Clock Fine Tuning */
DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
/* Complete calibration by forced measurement: */
DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
/*
* Calibration setup end
*/
/* MMDC init: */
DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
/*
* MDMISC: RALAT kept to the high level of 5.
* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
* Lower RALAT benefits:
* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
* to 3
* b. Small performence improvment
*/
DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
during MMDC set up */
DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
/* Mode register writes */
DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
device on CS0 */
DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
enter automatically to self-refresh while the
number of idle cycle reached. */
DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
the configuration bit as initialization is
complete) */
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