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/dts-v1/;
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
config {
silent_console = <0>;
};
gpio: gpio {};
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9";
spi-flash@0 {
reg = <0>;
compatible = "winbond,w25q64", "spi-flash";
memory-map = <0xff800000 0x00800000>;
};
};
lpc {
compatible = "intel,lpc";
#address-cells = <1>;
#size-cells = <1>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
/* This describes the flash memory within the EC */
#address-cells = <1>;
#size-cells = <1>;
flash@8000000 {
reg = <0x08000000 0x20000>;
erase-value = <0xff>;
};
};
};
};
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