blob: 17a715bac92e9fb840b08b2ae40f28dd81a0711d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
/*
* (C) Copyright 2016
* Vikas Manocha, <vikas.manocha@st.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
void clock_setup(int peripheral)
{
switch (peripheral) {
case USART1_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
break;
case GPIO_A_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
break;
case GPIO_B_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
break;
case GPIO_C_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
break;
case GPIO_D_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
break;
case GPIO_E_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
break;
case GPIO_F_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
break;
case GPIO_G_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
break;
case GPIO_H_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
break;
case GPIO_I_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
break;
case GPIO_J_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
break;
case GPIO_K_CLOCK_CFG:
setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
break;
default:
break;
}
}
|
