blob: 8e650862529e4046227753c4db3548b5c2fc441c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
/*
* (C) Copyright 2010-2013
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Tegra124 clock control definitions */
#ifndef _TEGRA124_CLOCK_H_
#define _TEGRA124_CLOCK_H_
#include <asm/arch-tegra/clock.h>
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
int tegra_plle_enable(void);
#endif /* _TEGRA124_CLOCK_H_ */
|
