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/*
* dts file for Xilinx ZynqMP ep108 development board
*
* (C) Copyright 2014 - 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-ep108-clk.dtsi"
/ {
model = "ZynqMP EP108";
aliases {
mmc0 = &sdhci0;
mmc1 = &sdhci1;
serial0 = &uart0;
spi0 = &qspi;
spi1 = &spi0;
spi2 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&gem0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
reg = <0>;
max-speed = <100>;
};
};
&gpio {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
eeprom@54 {
compatible = "at,24c64";
reg = <0x54>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
compatible = "at,24c64";
reg = <0x55>;
};
};
&nand0 {
status = "okay";
arasan,has-mdma;
num-cs = <1>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
reg = <0x0 0x0 0x400000>;
};
partition@1 { /* for testing purpose */
label = "nand-linux";
reg = <0x0 0x400000 0x1400000>;
};
partition@2 { /* for testing purpose */
label = "nand-device-tree";
reg = <0x0 0x1800000 0x400000>;
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
reg = <0x0 0x3000000 0x400000>;
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xFCC00000>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <10000000>;
partition@qspi-fsbl-uboot { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
partition@qspi-linux { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
partition@qspi-device-tree { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
partition@qspi-rootfs { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
};
};
&sata {
status = "okay";
ceva,broken-gen2;
/* SATA Phy OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
};
&sdhci0 {
status = "okay";
bus-width = <8>;
xlnx,mio_bank = <2>;
};
&sdhci1 {
status = "okay";
xlnx,mio_bank = <1>;
};
&spi0 {
status = "okay";
num-cs = <1>;
spi0_flash0: spi0_flash0@0 {
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
spi0_flash0@00000000 {
label = "spi0_flash0";
reg = <0x0 0x100000>;
};
};
};
&spi1 {
status = "okay";
num-cs = <1>;
spi1_flash0: spi1_flash0@0 {
compatible = "m25p80";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
spi1_flash0@00000000 {
label = "spi1_flash0";
reg = <0x0 0x100000>;
};
};
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
&usb1 {
status = "okay";
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
maximum-speed = "high-speed";
};
&watchdog0 {
status = "okay";
};
&xlnx_dp {
xlnx,max-pclock-frequency = <200000>;
};
&xlnx_dpdma {
xlnx,axi-clock-freq = <200000000>;
};
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