summaryrefslogtreecommitdiff
path: root/arch/arm/dts/tegra20-whistler.dts
blob: 447874674d72068b66c7d22217500fbd7b295443 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
/dts-v1/;

#include "tegra20.dtsi"

/ {
	model = "NVIDIA Tegra20 Whistler evaluation board";
	compatible = "nvidia,whistler", "nvidia,tegra20";

	chosen {
		stdout-path = &uarta;
	};

	aliases {
		i2c0 = "/i2c@7000d000";
		usb0 = "/usb@c5008000";
		mmc0 = "/sdhci@c8000600";
		mmc1 = "/sdhci@c8000400";
	};

	memory {
		device_type = "memory";
		reg = < 0x00000000 0x20000000 >;
	};

	serial@70006000 {
		clock-frequency = < 216000000 >;
	};

	i2c@7000d000 {
		status = "okay";
		clock-frequency = <100000>;

		pmic@3c {
			compatible = "maxim,max8907b";
			reg = <0x3c>;

			clk_32k: clock {
				compatible = "fixed-clock";
				/*
				 * leave out for now due to CPP:
				 * #clock-cells = <0>;
				 */
				clock-frequency = <32768>;
			};
		};
	};

	usb@c5008000 {
		status = "okay";
	};

	sdhci@c8000400 {
		status = "okay";
		wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
		bus-width = <8>;
	};

	sdhci@c8000600 {
		status = "okay";
		bus-width = <8>;
		non-removable;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk32k_in: clock@0 {
			compatible = "fixed-clock";
			reg=<0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

};