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/*
* Copyright (C) 2012 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/* First 4KB has trampoline code for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
#include "socfpga.dtsi"
/ {
soc {
clkmgr@ffd04000 {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
};
mmc0: dwmmc0@ff704000 {
num-slots = <1>;
broken-cd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
};
ethernet@ff702000 {
phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */
status = "okay";
};
sysmgr@ffd08000 {
cpu1-start-addr = <0xffd080c4>;
};
};
};
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