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/*
* Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/dts-v1/;
#include "rk3288-firefly.dtsi"
/ {
model = "Firefly-RK3288";
compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
chosen {
stdout-path = &uart2;
};
config {
u-boot,dm-pre-reloc;
u-boot,boot-led = "firefly:green:power";
};
};
&dmc {
rockchip,num-channels = <2>;
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
0x5 0x0>;
rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
0xa60 0x40 0x10 0x0>;
/* Add a dummy value to cause of-platdata think this is bytes */
rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>;
rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
};
&ir {
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
};
&pinctrl {
u-boot,dm-pre-reloc;
act8846 {
pmic_vsel: pmic-vsel {
rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
};
};
ir {
ir_int: ir-int {
rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pwm1 {
status = "okay";
};
&uart2 {
u-boot,dm-pre-reloc;
reg-shift = <2>;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&gpio3 {
u-boot,dm-pre-reloc;
};
&gpio8 {
u-boot,dm-pre-reloc;
};
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