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|
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx7d.dtsi"
/ {
model = "Freescale i.MX7 LPDDR3 19x19 ARM2 Board";
compatible = "fsl,imx7d-19x19-lpddr3-arm2", "fsl,imx7d";
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
status = "disabled";
volume-up {
label = "Volume Up";
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_sd1_vmmc: sd1_vmmc {
compatible = "regulator-fixed";
regulator-name = "VCC_SD1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
memory {
reg = <0x80000000 0x80000000>;
};
};
&adc1 {
vref-supply = <®_vref_1v8>;
status = "okay";
};
&cpu0 {
arm-supply = <&sw1a_reg>;
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
nand-on-flash-bbt;
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
pmic: pfuze3000@08 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx7d-19x19-lpddr3-arm2 {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
MX7D_PAD_SD1_WP__GPIO5_IO1 0x59
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59
MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
>;
};
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX7D_PAD_SD3_CLK__NAND_CLE 0x71
MX7D_PAD_SD3_CMD__NAND_ALE 0x71
MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
>;
};
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
>;
};
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x71
>;
};
pinctrl_weim_nor_1: weim_norgrp-1 {
fsl,pins = <
MX7D_PAD_EPDC_DATA08__EIM_OE 0x71
MX7D_PAD_EPDC_DATA09__EIM_RW 0x71
MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x71
MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x71
MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x75
/* data */
MX7D_PAD_LCD_DATA00__EIM_DATA0 0x7d
MX7D_PAD_LCD_DATA01__EIM_DATA1 0x7d
MX7D_PAD_LCD_DATA02__EIM_DATA2 0x7d
MX7D_PAD_LCD_DATA03__EIM_DATA3 0x7d
MX7D_PAD_LCD_DATA04__EIM_DATA4 0x7d
MX7D_PAD_LCD_DATA05__EIM_DATA5 0x7d
MX7D_PAD_LCD_DATA06__EIM_DATA6 0x7d
MX7D_PAD_LCD_DATA07__EIM_DATA7 0x7d
MX7D_PAD_LCD_DATA08__EIM_DATA8 0x7d
MX7D_PAD_LCD_DATA09__EIM_DATA9 0x7d
MX7D_PAD_LCD_DATA10__EIM_DATA10 0x7d
MX7D_PAD_LCD_DATA11__EIM_DATA11 0x7d
MX7D_PAD_LCD_DATA12__EIM_DATA12 0x7d
MX7D_PAD_LCD_DATA13__EIM_DATA13 0x7d
MX7D_PAD_LCD_DATA14__EIM_DATA14 0x7d
MX7D_PAD_LCD_DATA15__EIM_DATA15 0x7d
/* address */
MX7D_PAD_EPDC_DATA00__EIM_AD0 0x71
MX7D_PAD_EPDC_DATA01__EIM_AD1 0x71
MX7D_PAD_EPDC_DATA02__EIM_AD2 0x71
MX7D_PAD_EPDC_DATA03__EIM_AD3 0x71
MX7D_PAD_EPDC_DATA04__EIM_AD4 0x71
MX7D_PAD_EPDC_DATA05__EIM_AD5 0x71
MX7D_PAD_EPDC_DATA06__EIM_AD6 0x71
MX7D_PAD_EPDC_DATA07__EIM_AD7 0x71
MX7D_PAD_EPDC_BDR1__EIM_AD8 0x71
MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x71
MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x71
MX7D_PAD_EPDC_SDLE__EIM_AD11 0x71
MX7D_PAD_EPDC_SDOE__EIM_AD12 0x71
MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x71
MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x71
MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x71
MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x71
MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x71
MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x71
MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x71
MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x71
MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x71
MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x71
MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x71
MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x71
MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x71
>;
};
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
>;
};
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
>;
};
pinctrl_uart3dte_1: uart3dtegrp-1 {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79
MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
};
};
&iomuxc_lpsr {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_2>;
imx7d-19x19-lpddr3-arm2 {
pinctrl_hog_2: hoggrp-2 {
fsl,pins = <
MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14
MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
>;
};
};
};
&sdma {
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x28000000 0x08000000>;
status = "okay";
nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x08000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
/* for DTE mode, add below change */
/* fsl,dte-mode;*/
pinctrl-0 = <&pinctrl_uart3dte_1>;
};
&usbotg1 {
vbus-supply = <®_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
vbus-supply = <®_usb_otg2_vbus>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
no-1-8-v;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <®_sd1_vmmc>;
status = "okay";
};
|
