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/*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
aliases {
i2c3 = &i2c4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1150000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_STEP>,
<&clks IMX6QDL_CLK_PLL1_SW>,
<&clks IMX6QDL_CLK_PLL1_SYS>,
<&clks IMX6QDL_CLK_PLL1>,
<&clks IMX6QDL_PLL1_BYPASS>,
<&clks IMX6QDL_PLL1_BYPASS_SRC>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys", "pll1",
"pll1_bypass", "pll1_bypass_src";
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x14000000>;
linux,cma-default;
};
};
soc {
busfreq {
compatible = "fsl,imx_busfreq";
clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>,
<&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>,
<&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>,
<&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> ,
<&clks IMX6QDL_CLK_PLL3_PFD1_540M>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
interrupts = <0 107 0x04>, <0 112 0x4>;
interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
fsl,max_ddr_freq = <400000000>;
};
gpu@00130000 {
compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x0 0x0>, <0x0 0x8000000>;
reg-names = "iobase_3d", "iobase_2d",
"phys_baseaddr", "contiguous_mem";
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
<0 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_DUMMY>;
clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
"gpu2d_clk", "gpu3d_clk",
"gpu3d_shader_clk";
resets = <&src 0>, <&src 3>;
reset-names = "gpu3d", "gpu2d";
power-domains = <&gpc 1>;
};
ocram: sram@00905000 {
compatible = "mmio-sram";
reg = <0x00905000 0x1B000>;
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips1: aips-bus@02000000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
dcic2: dcic@020e8000 {
clocks = <&clks IMX6QDL_CLK_DCIC1 >,
<&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
clock-names = "dcic", "disp-axi";
};
pxp: pxp@020f0000 {
compatible = "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>;
clock-names = "pxp-axi", "disp-axi";
status = "disabled";
};
epdc: epdc@020f4000 {
compatible = "fsl,imx6dl-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>;
clock-names = "epdc_axi", "epdc_pix";
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
};
};
aips2: aips-bus@02100000 {
mipi_dsi: mipi@021e0000 {
compatible = "fsl,imx6dl-mipi-dsi";
reg = <0x021e0000 0x4000>;
interrupts = <0 102 0x04>;
gpr = <&gpr>;
clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
status = "disabled";
};
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6DL_CLK_I2C4>;
status = "disabled";
};
};
};
};
&ldb {
compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
<&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
clock-names = "ldb_di0", "ldb_di1",
"di0_sel", "di1_sel",
"di2_sel",
"ldb_di0_div_3_5", "ldb_di1_div_3_5",
"ldb_di0_div_7", "ldb_di1_div_7",
"ldb_di0_div_sel", "ldb_di1_div_sel";
};
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};
&vpu_fsl {
iramsize = <0>;
};
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