1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
|
/*
* Copyright (C) 2010 Linaro Limited
* John Rigby <john.rigby@linaro.org>
*
* Based on original from Linux kernel source and
* internal ST-Ericsson U-Boot source.
* (C) Copyright 2009 Alessandro Rubini
* (C) Copyright 2010 ST-Ericsson
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The MTU device has some interrupt control registers
* followed by 4 timers.
*/
/* The timers */
struct u8500_mtu_timer {
u32 lr; /* Load value */
u32 cv; /* Current value */
u32 cr; /* Control reg */
u32 bglr; /* ??? */
};
/* The MTU that contains the timers */
struct u8500_mtu {
u32 imsc; /* Interrupt mask set/clear */
u32 ris; /* Raw interrupt status */
u32 mis; /* Masked interrupt status */
u32 icr; /* Interrupt clear register */
struct u8500_mtu_timer pt[4];
};
/* bits for the control register */
#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */
#define MTU_CR_32BITS 0x02
#define MTU_CR_PRESCALE_1 0x00
#define MTU_CR_PRESCALE_16 0x04
#define MTU_CR_PRESCALE_256 0x08
#define MTU_CR_PRESCALE_MASK 0x0c
#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */
#define MTU_CR_ENA 0x80
/*
* The MTU is clocked at 133 MHz by default. (V1 and later)
*/
#define TIMER_CLOCK (133 * 1000 * 1000 / 16)
#define COUNT_TO_USEC(x) ((x) * 16 / 133)
#define USEC_TO_COUNT(x) ((x) * 133 / 16)
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
#define TIMER_LOAD_VAL 0xffffffff
/*
* MTU timer to use (from 0 to 3).
*/
#define MTU_TIMER 2
static struct u8500_mtu_timer *timer_base =
&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
/* macro to read the 32 bit timer: since it decrements, we invert read value */
#define READ_TIMER() (~readl(&timer_base->cv))
/* Configure a free-running, auto-wrap counter with /16 prescaler */
int timer_init(void)
{
writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
&timer_base->cr);
return 0;
}
ulong get_timer_masked(void)
{
/* current tick value */
ulong now = TICKS_TO_HZ(READ_TIMER());
if (now >= gd->lastinc) /* normal (non rollover) */
gd->tbl += (now - gd->lastinc);
else /* rollover */
gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
gd->lastinc = now;
return gd->tbl;
}
/* Delay x useconds */
void __udelay(ulong usec)
{
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
ulong now, last = READ_TIMER();
while (tmo > 0) {
now = READ_TIMER();
if (now > last) /* normal (non rollover) */
tmo -= now - last;
else /* rollover */
tmo -= TIMER_LOAD_VAL - last + now;
last = now;
}
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/*
* Emulation of Power architecture long long timebase.
*
* TODO: Support gd->tbu for real long long timebase.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* Emulation of Power architecture timebase.
* NB: Low resolution compared to Power tbclk.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
|
