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* dm: Add a system reset uclassSimon Glass2015-07-21-0/+63
| | | | | | | | | | | | | | | | It is common for system reset to be available at multiple levels in modern hardware. For example, an SoC may provide a reset option, and a board may provide its own reset for reasons of security or thoroughness. It is useful to be able to model this hardware without hard-coding the behaviour in the SoC or board. Also there is a distinction sometimes between resetting just the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting power. To achieve this, add a simple system reset uclass. It allows multiple devices to provide reset functionality and provides a way to walk through them, requesting a particular reset type until is it provided. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spl: Allow device tree/driver model in board_init_f()Simon Glass2015-07-21-0/+13
| | | | | | | | | | | | Add an spl_init() function that does basic init such that board_init_f() can use simple malloc(), device tree and driver model. Each one is set up only if enabled for SPL. Note: We really should refactor SPL such that there is a single board_init_f() and rename the existing weak board_init_f() functions provided by boards, calling them from the single board_init_f(). Signed-off-by: Simon Glass <sjg@chromium.org>
* lib: Add function to extract a number from the end of a stringSimon Glass2015-07-21-0/+26
| | | | | | | Split out the code in fdtdec which finds a number at the end of a string. It can be useful in other situations. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add rivest cipher 4 (rc4) implementationSimon Glass2015-07-21-0/+21
| | | | | | | Add an implementation of RC4. This will be used by Rockchip booting but may be useful in other situations. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add support for RAM driversSimon Glass2015-07-21-0/+39
| | | | | | | | Add support for a driver which sets up DRAM and can return information about the amount of RAM available. This is a first step towards moving RAM init to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pmic: Add functions to adjust PMIC registersSimon Glass2015-07-21-0/+34
| | | | | | | | | It is a common requirement to update some PMIC registers. Provide some simple convenience functions to do this. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* dm: power: Add a function to set up all regulatorsSimon Glass2015-07-21-0/+11
| | | | | | | | | The device tree provides information about which regulators should be on at boot, or always on. Use this to set them up automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* dm: pmic: Split output from functionSimon Glass2015-07-21-11/+27
| | | | | | | | | | | | | | | The regulator_autoset() function mixes printf() output and PMIC adjustment code. It provides a boolean to control the output. It is better to avoid missing logic and output, and this permits a smaller SPL code size. So split the output into a separate function. Also rename the function to have a by_name() suffix, since we would like to be able to pass a device when we know it, and thus avoid the name search. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* dm: power: Add regulator flags to centralise auto-set logicSimon Glass2015-07-21-0/+8
| | | | | | | | | Decide when the regulator is set up whether we want to auto-set the voltage or current. This avoids the complex logic spilling into the processing code. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* mmc: Add structure comments for dwmmcSimon Glass2015-07-21-1/+17
| | | | | | | It took a little while to figure this out, so this patch adds documentation to help the next person who needs to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Add an MMC uclassSimon Glass2015-07-21-0/+23
| | | | | | | Add basic support for MMC, providing a uclass which can set up an MMC device. This allows MMC drivers to move to using driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add support for LEDsSimon Glass2015-07-21-0/+52
| | | | | | | | | Add a simple uclass for LEDs, so that these can be controlled by the device tree and activated when needed. LEDs are referred to by their label. This implementation requires a driver for each type of LED (e.g GPIO, I2C). Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add support for generic system controllers (syscon)Simon Glass2015-07-21-0/+57
| | | | | | | | | | | Many SoCs have a number of system controllers which are dealt with as a group by a single driver. It is a pain to have to add lots of compatible strings and/or separate drivers for each. Instead we can identify the controllers by a number and request the address of the one we want. Add a simple implementation of this which can be used by SoC driver code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add support for register maps (regmap)Simon Glass2015-07-21-0/+72
| | | | | | | | | | | Add a simple implementaton of register maps, supporting only direct I/O for now. This can be enhanced later to support buses which have registers, such as I2C, SPI and PCI. It allows drivers which can operate with multiple buses to avoid dealing with the particulars of register access on that bus. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Add dm_gpio_request() to manually request a GPIOSimon Glass2015-07-21-0/+12
| | | | | | | This function can be used for testing to manually request a GPIO for use, without resorting to the legacy GPIO API. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Add dm_gpio_lookup_name() to look up a GPIO nameSimon Glass2015-07-21-0/+13
| | | | | | | Provide a driver-model function to look up a GPIO name. Make the standard function use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Correct device_get_child_by_of_offset() parameterSimon Glass2015-07-21-1/+1
| | | | | | This parameter is named 'seq' but should be named 'of_offset'. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Add a function to find any device from device treeSimon Glass2015-07-21-0/+14
| | | | | | | | | | | | In some rare cases it is useful to be able to locate a device given a device tree node offset. An example is when you have an alias that points to a node and you want to find the associated device. The device may be SPI, MMC or something else, but you don't need to know the uclass to find it. Add a function to do a global search for a device, given its device tree offset. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Move the tree/uclass dump code into its own fileSimon Glass2015-07-21-0/+6
| | | | | | | | | | In SPL it is sometimes useful to be able to obtain a dump of the current driver model state. Since commands are not available, provide a way to directly call the functions to output this information. Adjust the existing commands to use these functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* debug_uart: Remove use of asmlinkageSimon Glass2015-07-21-12/+10
| | | | | | | This does not actually help any current arch. For x86 it makes it harder to call (requires stack) and for ARM it has no effect. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add a way of checking the position of a structure memberSimon Glass2015-07-21-0/+11
| | | | | | | | | | | | U-Boot uses structures for hardware access so it is important that these structures are correct. Add a way of asserting that a structure member is at a particular offset. This can be created using the datasheet for the hardware. This implementation uses Static_assert() since BUILD_BUG_ON() only works within functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Add fdt_first/next_region() functionsSimon Glass2015-07-21-1/+238
| | | | | | | | These have been sent upstream but not accepted to libfdt. For now, bring these into U-Boot to enable fdtgrep to operate. We will use fdtgrep to cut device tree files down for SPL. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Add a function to remove unused strings from a device treeSimon Glass2015-07-21-0/+17
| | | | | | | | | | | | Property names are stored in a string table. When a node property is removed, the string table is not updated since other nodes may have a property with the same name. Thus it is possible for the string table to build up a number of unused strings. Add a function to remove these. This works by building a new device tree from the old one, adding strings one by one as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* mkimage: Display a better list of available image typesSimon Glass2015-07-21-0/+11
| | | | | | | | | | | Offer to display the available image types in help. Also, rather than hacking the genimg_get_type_id() function to display a list of types, do this in the tool. Also, sort the list. The list of image types is quite long, and hard to discover. Print it out when we show help information. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-07-20-75/+299
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| * armv8/ls2085ardb: Enable DSPI flash support for LS2085ARDBHaikun Wang2015-07-20-0/+8
| | | | | | | | | | | | | | Enable DSPI flash related configurations for LS2085ARDB. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: Enable DSPI flash support for LS2085AQDSHaikun Wang2015-07-20-0/+9
| | | | | | | | | | | | | | Enable DSPI flash related configurations. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls102xa: Add PSCI support for ls102xaWang Dongsheng2015-07-20-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/ls2085a: Increase kernel_size value in env variablePrabhakar Kushwaha2015-07-20-3/+3
| | | | | | | | | | | | | | | | | | Linux itb image size has been increased from 30MB. So updating kernel_size to 40MB in env variable. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/ls2085rdb: Export functions for standalone AQ FW load appsPrabhakar Kushwaha2015-07-20-1/+26
| | | | | | | | | | | | | | | | | | Export functions required by Aquntia PHY firmware load application. functions are memset, strcpy, mdelay, mdio_get_current_dev, phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: partition stream IDsStuart Yoder2015-07-20-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Update flibs to mc-0.6.0.1Prabhakar Kushwaha2015-07-20-52/+191
| | | | | | | | | | | | | | | | | | | | Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in dpio_attr. These are now offsets from the SoC QBMan portals base. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Autoload AOIP image from NOR flashJ. German Rivera2015-07-20-0/+6
| | | | | | | | | | | | | | | | | | Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: enable debug serverStuart Yoder2015-07-20-0/+1
| | | | | | | | | | | | Signed-off-by: Stuart Yoder <stuart.yoder at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvrPrabhakar Kushwaha2015-07-20-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | The agreed split of the top of memory is 256M for debug server and 256M for MC. This patch implements the split. In addition, the MC mem must be 512MB aligned, so the amount of memory to hide must be 512MB to achieve that alignment. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Fix SPD address error on early boardsYork Sun2015-07-20-2/+2
| | | | | | | | | | | | | | | | | | Board rev C and earlier has duplicated SPD address on 2nd DDR controller slots. It is fixed on rev D and later. SPD addresses need to be updated accordingly. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * driver/ddr/fsl: Add a hook to update SPD addressYork Sun2015-07-20-0/+3
| | | | | | | | | | | | | | | | In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
| * armv8/ls2085a: Avoid hard-coding for board name printPrabhakar Kushwaha2015-07-20-5/+0
| | | | | | | | | | | | | | | | | | | | | | LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A personlities. Instead of hard-coding, board name should change as per selected personality. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Increase the supported kernel sizeBhupesh Sharma2015-07-20-5/+8
| | | | | | | | | | | | | | | | | | | | | | Increases the kernel size supported for LS2085A platforms:- - Update environment variables - Add ramdisk_size in bootargs env variable - Define CONFIG_SYS_BOOTM_LEN to 64MB Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085rdb: Update PCA9547PW slave addressPrabhakar Kushwaha2015-07-20-2/+2
| | | | | | | | | | | | | | | | Primary Mux on I2C1 controller has slave address as 0x75. So update its address. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Update LS2085a PCIe compatiblePrabhakar Kushwaha2015-07-20-1/+2
| | | | | | | | | | | | | | | | | | Compatible field "fsl,20851a-pcie" is not correct. So update it to "fsl,ls2085a-pcie" Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Enable "date" command for QDS and RDBPriyanka Jain2015-07-20-0/+2
| | | | | | | | | | | | | | | | Enable "date" command for QDS and RDB boards Signed-off-by: Priyanka Jain <Priyanka.Jain at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: add hwconfig setting for eSDHCYangbo Lu2015-07-20-0/+2
| | | | | | | | | | | | | | | | | | Add hwconfig setting for eSDHC since it shares some pins with other IP block. Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Add eth & phy firmware loading supportPrabhakar Kushwaha2015-07-20-0/+23
| | | | | | | | | | | | | | | | | | | | Add support for board eth initialization and support for loading phy firmware. PHY firmware needs to be loaded from board_eth_init() because all the MACs are not initialized by ldpaa_eth driver. Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | libfdt: fix description of fdt_get_string()Masahiro Yamada2015-07-20-1/+1
| | | | | | | | | | | | | | | | | | Looks like this comment was copied from that of fdt_get_string_index(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: 5094eb408a5d ("fdt: Add functions to retrieve strings") Acked-by: Simon Glass <sjg@chromium.org>
* | fdt: prevent clearing memory node if there are no banksAndre Przywara2015-07-20-0/+26
|/ | | | | | | | | | | | | Avoid clearing the reg property in the memory DT node if no memory banks have been specified for a board (CONFIG_NR_DRAM_BANKS == 0). This allows boards to let U-Boot skip the DT memory tinkering in case other firmware has already setup the node properly before. This should be safe as all callers of fdt_fixup_memory_banks that use a computed <banks> value put at least 1 in there. Add some documentation comments to the header file. Signed-off-by: Andre Przywara <osp@andrep.de> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-15-27/+39
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| * pci: Configure expansion ROM during auto config processBin Meng2015-07-14-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-0/+1
| | | | | | | | | | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: x86: minnowmax: Move PCI to use driver modelSimon Glass2015-07-14-0/+1
| | | | | | | | | | | | | | | | | | Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
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