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author | Simon Glass <sjg@chromium.org> | 2015-06-23 15:39:13 -0600 |
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committer | Simon Glass <sjg@chromium.org> | 2015-07-21 17:39:29 -0600 |
commit | f9917454d55caf3dafa41b27d8d8274716433a4c (patch) | |
tree | 81f7c0e4cb2a9c3e04eab94ef17da21f2de1192f /include | |
parent | 92a655c326b22de58dcd5371ca1a62fdc57f8e04 (diff) | |
download | u-boot-imx-f9917454d55caf3dafa41b27d8d8274716433a4c.zip u-boot-imx-f9917454d55caf3dafa41b27d8d8274716433a4c.tar.gz u-boot-imx-f9917454d55caf3dafa41b27d8d8274716433a4c.tar.bz2 |
dm: Add a system reset uclass
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.
To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/dm/uclass-id.h | 1 | ||||
-rw-r--r-- | include/reset.h | 62 |
2 files changed, 63 insertions, 0 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 93a3857..b993fc0 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -44,6 +44,7 @@ enum uclass_id { UCLASS_PCI_GENERIC, /* Generic PCI bus device */ UCLASS_PMIC, /* PMIC I/O device */ UCLASS_REGULATOR, /* Regulator device */ + UCLASS_RESET, /* Reset device */ UCLASS_RTC, /* Real time clock device */ UCLASS_SERIAL, /* Serial UART */ UCLASS_SPI, /* SPI bus */ diff --git a/include/reset.h b/include/reset.h new file mode 100644 index 0000000..d29e108 --- /dev/null +++ b/include/reset.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RESET_H +#define __RESET_H + +enum reset_t { + RESET_WARM, /* Reset CPU, keep GPIOs active */ + RESET_COLD, /* Reset CPU and GPIOs */ + RESET_POWER, /* Reset PMIC (remove and restore power) */ + + RESET_COUNT, +}; + +struct reset_ops { + /** + * request() - request a reset of the given type + * + * Note that this function may return before the reset takes effect. + * + * @type: Reset type to request + * @return -EINPROGRESS if the reset has been started and + * will complete soon, -EPROTONOSUPPORT if not supported + * by this device, 0 if the reset has already happened + * (in which case this method will not actually return) + */ + int (*request)(struct udevice *dev, enum reset_t type); +}; + +#define reset_get_ops(dev) ((struct reset_ops *)(dev)->driver->ops) + +/** + * reset_request() - request a reset + * + * @type: Reset type to request + * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device + */ +int reset_request(struct udevice *dev, enum reset_t type); + +/** + * reset_walk() - cause a reset + * + * This works through the available reset devices until it finds one that can + * perform a reset. If the provided reset type is not available, the next one + * will be tried. + * + * If this function fails to reset, it will display a message and halt + * + * @type: Reset type to request + */ +void reset_walk(enum reset_t type); + +/** + * reset_cpu() - calls reset_walk(RESET_WARM) + */ +void reset_cpu(ulong addr); + +#endif |