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* fdt: add new fdt address parsing functionsStephen Warren2015-09-15-8/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fdtdec_get_addr_size() hard-codes the number of cells used to represent an address or size in DT. This is incorrect in many cases depending on the DT binding for a particular node or property (e.g. it is incorrect for the "reg" property). In most cases, DT parsing code must use the properties #address-cells and #size-cells to parse addres properties. This change splits up the implementation of fdtdec_get_addr_size() so that the core logic can be used for both hard-coded and non-hard-coded cases. Various wrapper functions are implemented that support cases where hard-coded cell counts should or should not be used, and where the client does and doesn't know the parent node ID that contains the properties #address-cells and #size-cells. dev_get_addr() is updated to use the new functions. Core functionality in fdtdec_get_addr_size_fixed() is widely tested via fdtdec_get_addr_size(). I tested fdtdec_get_addr_size_auto_noparent() and dev_get_addr() by manually modifying the Tegra I2C driver to invoke them. Much of the core implementation of fdtdec_get_addr_size_fixed(), fdtdec_get_addr_size_auto_parent(), and fdtdec_get_addr_size_auto_noparent() comes from Thierry Reding's previous commit "fdt: Fix fdtdec_get_addr_size() for 64-bit". Based-on-work-by: Thierry Reding <treding@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped #define DEBUG at the top of fdtdec.c: Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: dw_mmc: Probe the MMC from OFMarek Vasut2015-09-04-0/+1
| | | | | | | | | | | | | Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files. This patch now also removes previous temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* dm: tpm: Convert I2C driver to driver modelSimon Glass2015-08-31-2/+0
| | | | | | | | | Convert the tpm_tis_i2c driver to use driver model and update boards which use it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-18-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROLMasahiro Yamada2015-08-18-1/+1
| | | | | | | | | | | | | | | | | | | As we discussed a couple of times, negative CONFIG options make our life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ... and here is another one. Now, there are three boards enabling OF_CONTROL on SPL: - socfpga_arria5_defconfig - socfpga_cyclone5_defconfig - socfpga_socrates_defconfig This commit adds CONFIG_SPL_OF_CONTROL for them and deletes CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert the logic. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* fdtdec: fix OF_CONTROL switchMasahiro Yamada2015-08-18-1/+1
| | | | | | | | There is no case where defined(SPL_DISABLE_OF_CONTROL) is true. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-14-0/+2
| | | | | | | | | | | | | | | | | Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: socfpga: misc: Reset ethernet from OFMarek Vasut2015-08-08-0/+1
| | | | | | | | | | | Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* lib/fdtdec: Fix fdt_addr_t and fdt_size_t typedefYork Sun2015-08-06-4/+2
| | | | | | | | | fdt_addr_t is a physical address. It can be either 64-bit or 32-bit, depending on the architecture. It should be phys_addr_t instead of u64 or u32. Similarly, fdt_size_t is changed to phys_size_t. Signed-off-by: York Sun <yorksun@freescale.com> CC: Simon Glass <sjg@chromium.org>
* dts: Drop unused compatible ID for the NXP video bridgeSimon Glass2015-08-05-1/+0
| | | | | | This has moved to driver model so we can drop the fdtdec support. Signed-off-by: Simon Glass <sjg@chromium.org>
* video: Remove the old parade driverSimon Glass2015-08-05-1/+0
| | | | | | | We have a new one which uses driver model and device tree configuration. Remove the old one. Signed-off-by: Simon Glass <sjg@chromium.org>
* power: Remove old TPS65090 driversSimon Glass2015-08-05-1/+0
| | | | | | | Remove the old drivers (both the normal one and the cros_ec one) now that we have new drivers that use driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-0/+3
| | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* dm: usb: tegra: Drop legacy USB codeSimon Glass2015-06-10-3/+0
| | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: Move CONFIG_SANDBOX_SERIAL to KconfigSimon Glass2015-06-10-0/+6
| | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-0/+1
| | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-0/+1
| | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* tegra: video: Support serial output resource (SOR) on tegra124Simon Glass2015-05-13-0/+3
| | | | | | | | | The SOR is required for talking to eDP LCD panels. Add a driver for this which will be used by the DisplayPort driver. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* fdt: Add binding decode function for display-timingsSimon Glass2015-05-13-0/+77
| | | | | | | | This is useful for display parameters. Add a simple decode function to read from this device tree node. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: usb: exynos: Drop legacy USB codeSimon Glass2015-05-06-2/+0
| | | | | | Drop the code that doesn't use driver model for USB. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Select device tree control correctly for SPLSimon Glass2015-04-23-0/+10
| | | | | | | Some boards will not use device tree for SPL even with driver model. Add the logic to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Rename setup_fdt() and make it prepare alsoSimon Glass2015-04-23-1/+1
| | | | | | | There is little reason to split these two functions. Bring them together which simplifies the init sequence. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: sandbox: Move setup code from board_f to fdtdecSimon Glass2015-04-23-0/+6
| | | | | | | We want to be able to set up the device tree in SPL, so move this code to a common place. Signed-off-by: Simon Glass <sjg@chromium.org>
* cros_ec: exynos: Match up device tree with kernel versionSimon Glass2015-04-18-1/+0
| | | | | | | | | | | The U-Boot device trees are slightly different in a few places. Adjust them to remove most of the differences. Note that U-Boot does not support the concept of interrupts as distinct from GPIOs, so this difference remains. For sandbox, use the same keyboard file as for ARM boards and drop the host emulation bus which seems redundant. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Drop LPC compatible string in fdtdecSimon Glass2015-04-18-1/+0
| | | | | | | This is not needed now that we have moved chromebook_link and cros_ec to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: cros_ec: Drop compatible string in fdtdecSimon Glass2015-04-18-1/+0
| | | | | | This is not needed now that we have moved to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-18-0/+1
| | | | | | | | | | | | The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Tighten up error handling in fdtdec_get_pci_addr()Simon Glass2015-04-16-1/+3
| | | | | | | | | | | | | This function returns -ENOENT when the property is missing (which the caller might forgive) and also when the property is present but incorrectly formatted (which many callers would like to report). Update the error return value to allow these different situations to be distinguished. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* fdt: Export fdtdec_get_number() for general useSimon Glass2015-04-16-0/+11
| | | | | | | This function is missing a prototype but is more widey useful. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* fdtdec: Improve fdtdec_get_pci_bdf() documentationBin Meng2015-03-24-1/+4
| | | | | | | | Add the description that how the compatible property is involved in the fdtdec_get_pci_bdf() documentation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: UniPhier: adjust device trees for business transferMasahiro Yamada2015-03-15-1/+1
| | | | | | | Panasonic's System LSI products, UniPhier SoC family, have been transferred to Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* usb: UniPhier: add UniPhier on-chip xHCI host driver supportMasahiro Yamada2015-03-01-0/+1
| | | | | | | Support xHCI host driver used on Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* fdtdec: Add compatible id and string for Intel Quark MRCBin Meng2015-02-06-0/+1
| | | | | | | | Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can decode Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: exynos: Drop unused COMPAT features for SPISimon Glass2015-01-29-1/+0
| | | | | | | This has moved to driver model so we don't need the fdtdec support. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: tegra: Drop unused COMPAT features for I2C, SPISimon Glass2015-01-29-6/+0
| | | | | | These have moved to driver model so we don't need the fdtdec support. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: fdt: Remove the old GPIO functionsSimon Glass2015-01-29-77/+0
| | | | | | | Now that we support device tree GPIO bindings directly in the driver model GPIO uclass we can remove these functions. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: fdt: Add a function to decode phandles with argumentsSimon Glass2015-01-29-0/+53
| | | | | | | | | | | For GPIOs and other functions we want to look up a phandle and then decode a list of arguments for that phandle. Each phandle can have a different number of arguments, specified by a property in the target node. This is the "#gpio-cells" property for GPIOs. Add a function to provide this feature, taken modified from Linux 3.18. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add compatible string for Intel ICH9 SPI controllerSimon Glass2015-01-23-0/+1
| | | | | | | Add this to the enum so that we can use the various fdtdec functions. A later commit will move this driver to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* fdt: Add several apis to decode pci device nodeBin Meng2015-01-13-11/+98
| | | | | | | | | | | | | | This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including: - fdtdec_get_pci_addr() for encoded pci address - fdtdec_get_pci_vendev() for vendor id and device id - fdtdec_get_pci_bdf() for pci device bdf triplet - fdtdec_get_pci_bar32() for pci device register bar Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
* pci: tegra: Add Tegra PCIe driverThierry Reding2014-12-18-0/+3
| | | | | | | | | | | | | | | Add support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports with a total of 5 lanes. This is based on the Linux kernel driver, originally submitted upstream by Mike Rapoport. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Implement XUSB pad controllerThierry Reding2014-12-18-0/+2
| | | | | | | | | | | | | | | This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* power: Add AMS AS3722 PMIC supportThierry Reding2014-12-18-0/+1
| | | | | | | | | The AS3722 provides a number of DC/DC converters and LDOs as well as 8 GPIOs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-fdtTom Rini2014-12-01-11/+0
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| * fdt: remove fdtdec_get_alias_node() functionMasahiro Yamada2014-11-27-11/+0
| | | | | | | | | | | | | | | | | | | | The fdt_path_offset() checks an alias too. fdtdec_get_alias_node(blob, "foo") is equivalent to fdt_path_offset(blob, "foo"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2014-12-01-0/+3
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| * x86: Add initial video device init for Intel GMASimon Glass2014-11-25-0/+1
| | | | | | | | | | | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+1
| | | | | | | | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+1
| | | | | | | | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-fdtTom Rini2014-11-26-5/+48
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| * fdt: Add a function to decode a named memory regionSimon Glass2014-11-21-0/+27
| | | | | | | | | | | | | | | | Permit decoding of a named memory region from the device tree. This allows easy run-time configuration of the address of on-chip SRAM, SDRAM, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-11-05 16:21:05 +0000