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* mpc83xx: add support for the MPC8360E-RDKAnton Vorontsov2008-01-10-0/+538
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is MPC8360E based board with: - 256MB fixed SDRAM; - 8MB Intel Strata NOR flash; - StMICRO 64MiB NAND flash; - two 10/100/1000 ethernet ports connected via Broadcom BCM5481 PHYs; - two 10/100 ethernet ports connected via National DP83848 PHYs; - one PCI and one miniPCI slots; - four serial ports (two NS16550-compatible, two UCCs); - four USB ports working through MPC8360E "FHCI" USB controller; - Fujitsu MB86277 graphics controller; - Analog to Digital Converter/Touchscreen controller, AD7843 connected to SPI. Features not supported in this patch are: - StMICRO 64MiB NAND flash (patch sent); - MINT framebuffer initialization (patch is pending); - Fetching production information from the EEPROM via I2C; - FHCI USB; - Two slow UCCs used as RS-485 UARTs. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: add missing CONFIG_HAS_ETH0 definesKim Phillips2008-01-10-0/+3
| | | | | | | | | the new libfdt code only updates eth0 if CONFIG_HAS_ETH0 is defined; add the define to the missing board configs. Thanks to Emilian Medve for finding this. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Remove cache config from ATUM8548 and sbc8548 configsAndy Fleming2008-01-09-14/+0
| | | | | | | These boards weren't updated by Kumar's config patch because they weren't in the tree, yet. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-112/+0
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add support for ATUM8548 (updated)robert lazarski2008-01-09-0/+465
| | | | | | Add support for Instituto Atlantico's ATUM8548 board Signed-off-by: robert lazarski <robertlazarski@gmail.com>
* mpc85xx: Add support for SBC8548 (updated)Joe Hamman2008-01-09-0/+576
| | | | | | Add support for Wind River's SBC8548 reference board. Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
* trivial: fix consequences of a bad mergeGuennadi Liakhovetski2008-01-09-1/+0
| | | | | | Fix what looks like a merge artifact. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
* fix comments with new drivers organizationMarcel Ziswiler2008-01-09-8/+8
| | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* Improve configuration of FPGA subsystemMatthias Fuchs2008-01-09-3/+9
| | | | | | | | | | | | | This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-01-09-9/+9
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-armWolfgang Denk2008-01-09-0/+238
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| * Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2008-01-07-1300/+3449
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| * | Remove warnings re CONFIG_EXTRA_ENV_SETTINGSPeter Pearse2007-11-15-9/+9
| | | | | | | | | | | | Remove warnings re onenand_read() & write()
| * | Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-11-15-1/+1
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| * | | Add apollon board supportPeter Pearse2007-11-09-0/+238
| | | | | | | | | | | | | | | | Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk2008-01-09-53/+624
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| * | | | mpc83xx: convert to using do_fixup_*()Kim Phillips2008-01-08-45/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | convert to using simpler mpc85xx style fdt update code; streamline by eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm the old school FLAT_TREE code from 83xx (since the sbc8349 was just converted over to using libfdt). Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | sbc8349: enable libfdt by default on WRS SBC8349 board.Paul Gortmaker2008-01-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make libfdt the default for the WRS SBC8349 board. Parallel of commit 35cc4e4823668e8745854899cfaedd4489beb0ef done for the other 83xx based boards. Also fix a typo in CONFIG_PCI. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| * | | | mpc83xx: Remove CONFIG options related to OF that we dont use (on 837x)Kim Phillips2008-01-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | Remove CONFIG options related to OF that we dont useKumar Gala2008-01-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8360E MDS config defined: CONFIG_OF_HAS_BD_T CONFIG_OF_HAS_UBOOT_ENV Which we don't use or ever needed. This seems like copy-paste feature creep. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | mpc83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions for 837xKim Phillips2008-01-08-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x. This change guarantees that the environment will be located on the first flash sector after the U-Boot image. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | | mpc83xx: Add the support of MPC837xEMDS boardDave Liu2008-01-08-0/+605
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | | | 83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitionsTimur Tabi2008-01-08-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the currently-defined 83xx boards. This change guarantees that the environment will be located on the first flash sector after the U-Boot image. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | | | Merge branch 'master' of /home/wd/git/u-boot/master/Wolfgang Denk2008-01-09-0/+1
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| * | | | | Fix problems with usb storage devices on MPC5200 /TQM5200Markus Klotzbücher2008-01-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC5200 OHCI controller operates in big endian, so CFG_OHCI_BE_CONTROLLER must be defined for it to work properly. Signed-off-by: Markus Klotzbuecher <mk@denx.de>
* | | | | | Merge branch 'lwmon5-no-ocm'Stefan Roese2008-01-09-7/+12
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| * | | | | | ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymoreStefan Roese2008-01-09-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch configures the LWMON5 port to use d-cache as init-ram and the unused GPT0_COMP6 as POST WORD storage. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | | ppc4xx: Disable error message when no NAND chip is installed on PMC440Matthias Fuchs2008-01-09-0/+3
| |/ / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CFG_NAND_QUIET_TEST option to disable error message when no NAND chip is installed on PMC440 boards. Disable a couple of config defines that are only used for NAND_U_BOOT. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | | | | Merge branch 'inka4x0-ng' of /home/m8/git/u-boot/Wolfgang Denk2008-01-08-13/+20
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| * | | | | [INKA4x0] NG hardware: flash supportMarian Balakowicz2007-11-15-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disabled and remove inka4x0 custom flash driver, use CFI flash driver instead. Signed-off-by: Marian Balakowicz <m8@semihalf.com>
| * | | | | [INKA4x0] NG hardware: SDRAM supportMarian Balakowicz2007-11-15-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for three new DDR chips that may be present on a NG INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT. Cleanup board/inka4x0/mt48lc16m16a2-75.h file. Signed-off-by: Marian Balakowicz <m8@semihalf.com>
| * | | | | [INKA4x0] NG hardware: platform code updateMarian Balakowicz2007-11-15-2/+3
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Cleanup compile warnings. - Add missing '\0' in default environment. - Increase CFG_MONITOR_LEN to 256 KiB. - Add required CFG_USE_PPCENV. Signed-off-by: Marian Balakowicz <m8@semihalf.com>
* | | | | Merge branch 'katmai-ddr-gda'Stefan Roese2008-01-05-0/+1
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| * | | | | ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setupStefan Roese2008-01-05-0/+1
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Korat boardLawrence R. Johnson2008-01-04-1/+152
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* | | | | ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia boardLawrence R. Johnson2008-01-04-0/+77
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: this patch changes the configuration of some GPIO registers: Register Old Value New Value --------------- ---------- ---------- DCR GPIO0_TCR 0x0000000F 0x0000F0CF DCR GPIO0_TSRH 0x55005000 0x00000000 DCR GPIO1_TCR 0xC2000000 0xE2000000 DCR GPIO1_TSRL 0x0C000000 0x00200000 DCR GPIO1_ISR2L 0x00050000 0x00110000 Signed-off-by: Larry Johnson <lrj@acm.org>
* | | | Don't slam #undef DEBUG in the 8641HPCN config file.Jon Loeliger2008-01-03-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Doing so prevents it from being individually set and useful in other files. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | | Convert MPC8641HPCN to use libfdt.Jon Loeliger2008-01-03-12/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assumes the presence of the aliases node in the DTS to locate the ethernet, pci and serial nodes for fixups. Use consistent fdtaddr and fdtfile in environment variables. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | | Merge commit 'wd/master'Jon Loeliger2008-01-03-1275/+2736
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| * | | ppc4xx: Complete PMC440 board supportMatthias Fuchs2007-12-28-0/+522
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch brings the PMC440 board configuration file. Finally it enables the PMC440 board support. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * | | ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updatesMatthias Fuchs2007-12-28-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add EEPROM write protection for esd PLU405 boards. - initialize NAND GPIOs - use correct io accessors - cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * | | ppc4xx: Maintenance patch for VOH405 boardsMatthias Fuchs2007-12-28-20/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add EEPROM write protection - initialize NAND GPIOs - use correct io accessors - slow down I2C clock to 100kHz - enable ext. I2C bus - cleanup Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
| * | | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into for-1.3.2-ver2Stefan Roese2007-12-27-341/+840
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| | * \ \ Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2007-12-27-98/+157
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| | | * | | Some configuration updates for the TQM5200 based TB5200 board:Martin Krause2007-12-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - enable command line history - increase malloc space (because of bigger flash sectors) Signed-off-by: Martin Krause <martin.krause@tqs.de>
| | | * | | TQM8xx: use the CFI flash driver on all TQM8xx boardsMartin Krause2007-12-27-64/+116
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Krause <martin.krause@tqs.de>
| | | * | | TQM885D: adjust for doubled flash sector size + some minor fixesMartin Krause2007-12-27-7/+13
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Krause <martin.krause@tqs.de>
| | | * | | TQM885D: Exchanged SDRAM timing by a more relaxed timing.Jens Gehrlein2007-12-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAS-Latency=2, Write Recovery Time tWR=2 The max. supported bus frequency is 66 MHz. Therefore, changed threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. Signed-off-by: Martin Krause <martin.krause@tqs.de>
| | | * | | TQM885D: use calculated cpuclk instead of measuring itMartin Krause2007-12-27-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the TQM885D the measurement of cpuclk with the PIT reference timer ist not necessary. Since all module variants use the same external 10 MHz oscillator, the cpuclk only depends on the PLL configuration - which is readable by software. Signed-off-by: Martin Krause <martin.krause@tqs.de>
| | | * | | TQM885D: fix SDRAM refreshJens Gehrlein2007-12-27-16/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At 133 MHz the current SDRAM refresh rate is too fast (measured 4 * 1.17 us). CFG_MAMR_PTA changes from 39 to 128. This result in a refresh rate of 4 * 7.8 us at the default clock 66 MHz. At 133 MHz the value will be then 4 * 3.8 us. This is a compromise until a new method is found to adjust the refresh rate. Signed-off-by: Martin Krause <martin.krause@tqs.de>
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