| Commit message (Collapse) | Author | Age | Lines |
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These boards weren't updated by Kumar's config patch because they
weren't in the tree, yet.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.
Also, minor cleanup in cache.h to make the code a bit more readable.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add support for Instituto Atlantico's ATUM8548 board
Signed-off-by: robert lazarski <robertlazarski@gmail.com>
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Add support for Wind River's SBC8548 reference board.
Signed-off by: Joe Hamman <joe.hamman@embeddedspecialties.com>
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Fix what looks like a merge artifact.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
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Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
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This patch removes the FPGA subsystem configuration through
the CONFIG_FPGA bitmask configuration option.
See README for the new options:
CONFIG_FPGA,
CONFIG_FPGA_<vendor>,
CONFIG_FPGA_<family>
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Remove warnings re onenand_read() & write()
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Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
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convert to using simpler mpc85xx style fdt update code; streamline by
eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm
the old school FLAT_TREE code from 83xx (since the sbc8349 was just
converted over to using libfdt).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Make libfdt the default for the WRS SBC8349 board.
Parallel of commit 35cc4e4823668e8745854899cfaedd4489beb0ef
done for the other 83xx based boards. Also fix a typo in CONFIG_PCI.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The MPC8360E MDS config defined:
CONFIG_OF_HAS_BD_T
CONFIG_OF_HAS_UBOOT_ENV
Which we don't use or ever needed. This seems like copy-paste feature creep.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x.
This change guarantees that the environment will be located on the
first flash sector after the U-Boot image.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
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Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the
currently-defined 83xx boards. This change guarantees that the environment
will be located on the first flash sector after the U-Boot image.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The MPC5200 OHCI controller operates in big endian, so
CFG_OHCI_BE_CONTROLLER must be defined for it to work properly.
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
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This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.
Signed-off-by: Stefan Roese <sr@denx.de>
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Add CFG_NAND_QUIET_TEST option to disable error message when
no NAND chip is installed on PMC440 boards.
Disable a couple of config defines that are only used for NAND_U_BOOT.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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Disabled and remove inka4x0 custom flash driver, use CFI flash
driver instead.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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Add support for three new DDR chips that may be present on a NG
INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT.
Cleanup board/inka4x0/mt48lc16m16a2-75.h file.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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- Cleanup compile warnings.
- Add missing '\0' in default environment.
- Increase CFG_MONITOR_LEN to 256 KiB.
- Add required CFG_USE_PPCENV.
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
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On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Larry Johnson <lrj@acm.org>
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Note: this patch changes the configuration of some GPIO registers:
Register Old Value New Value
--------------- ---------- ----------
DCR GPIO0_TCR 0x0000000F 0x0000F0CF
DCR GPIO0_TSRH 0x55005000 0x00000000
DCR GPIO1_TCR 0xC2000000 0xE2000000
DCR GPIO1_TSRL 0x0C000000 0x00200000
DCR GPIO1_ISR2L 0x00050000 0x00110000
Signed-off-by: Larry Johnson <lrj@acm.org>
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Doing so prevents it from being individually set
and useful in other files.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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Assumes the presence of the aliases node in the DTS to
locate the ethernet, pci and serial nodes for fixups.
Use consistent fdtaddr and fdtfile in environment variables.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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This patch brings the PMC440 board configuration file.
Finally it enables the PMC440 board support.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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- add EEPROM write protection for esd PLU405 boards.
- initialize NAND GPIOs
- use correct io accessors
- cleanup
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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- add EEPROM write protection
- initialize NAND GPIOs
- use correct io accessors
- slow down I2C clock to 100kHz
- enable ext. I2C bus
- cleanup
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
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- enable command line history
- increase malloc space (because of bigger flash sectors)
Signed-off-by: Martin Krause <martin.krause@tqs.de>
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Signed-off-by: Martin Krause <martin.krause@tqs.de>
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Signed-off-by: Martin Krause <martin.krause@tqs.de>
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CAS-Latency=2, Write Recovery Time tWR=2
The max. supported bus frequency is 66 MHz. Therefore, changed
threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
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On the TQM885D the measurement of cpuclk with the PIT reference
timer ist not necessary. Since all module variants use the same
external 10 MHz oscillator, the cpuclk only depends on the PLL
configuration - which is readable by software.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
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At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 128. This result
in a refresh rate of 4 * 7.8 us at the default clock
66 MHz. At 133 MHz the value will be then 4 * 3.8 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
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Signed-off-by: Martin Krause <martin.krause@tqs.de>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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