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* | | net: cpsw: Add support to drive gpios for ethernet to be functionalVignesh R2016-08-08-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA72 EVM, cpsw slaves may be muxed with other modules. This selection is controlled by a pcf gpio line. Add support for cpsw driver to acquire mode-gpios and select the appropriate slave using gpio APIs. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | | gpio: Add driver for TI PCF8575 I2C GPIO expanderVignesh R2016-08-08-0/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a 16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. The I/Os should be high before being used as inputs. Read the device documentation for more details[1]. This driver is based on pcf857x driver available in Linux v4.7 kernel. It supports basic reading and writing of gpio pins. [1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | | spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max valueChin Liang See2016-08-07-2/+5
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensuring the baudrate divisor value doesn't exceed the max value in the calculation.It will be capped at max value to ensure the correct value being written into the register. Example of the existing bug is when calculated div = 16. After and with the mask, the value written to register is actually 0 (register field for baudrate divisor). With this fix, the value written is now 15 which is max value for baudrate divisor. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jteki@openedev.com> Cc: Dinh Nguyen <dinguyen@altera.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-08-06-16/+848
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| * | rockchip: remove log2 reimplementation from clock driversHeiko Stübner2016-08-05-14/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The already available ilog2 function does exactly the same in the common case than the log2 function the current clock-driver reimplement. So, simply move to that one. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
| * | clock: rk3399: add support for dwmmc 400KKever Yang2016-08-05-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | MMC core will use 400KHz for card initialize first and then switch to higher frequency like 50MHz, we need to support both 400KHz and about 50MHz for dwmmc controller. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | move: rockchip: move clock drivers into a subdirectoryHeiko Stübner2016-08-05-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org> Updated for rk3399: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rk3399: add basic soc driverKever Yang2016-08-05-0/+820
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | zynq_sdhci.c: Fix warning in arasan_sdhci_probeTom Rini2016-08-05-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We no longer need to set 'caps' as it's not passed to sdhci_setup_cfg anymore. Fixes: 14bed52d276a ("mmc: sdhci: remove the unnecessary arguments for sdhci_setup_cfg") Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-08-05-8/+39
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| * | | ARM: tegra: adapt to latest HSP DT bindingStephen Warren2016-08-04-8/+39
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT binding for the Tegra186 HSP module apparently wasn't quite final when I posted initial U-Boot support for it. Add the final DT binding doc and adapt all code and DT files to match it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | mmc: sdhci: fix the compiler warning when disable CONFIG_MMC_SDMAJaehoon Chung2016-08-05-1/+1
| | | | | | | | | | | | | | | | | | | | | When disabled CONFIG_MMC_SDMA, variable caps didn't use. This patch fixes the compiler error for -Wunused-but-set-variable Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | mmc: dw_mmc: fix data starvation by host timeout under FIFO modeXu Ziyuan2016-08-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes data starvation by host timeout(HTO) error interrupt which occurred under FIFO mode transfer on rk3036 board. The former implement, the actual bytes were transmitted may be less than should be. The size will still subtract value of len in case of there is no receive/transmit FIFO data request interrupt. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | mmc: dw_mmc: transfer proper bytes to FIFOXu Ziyuan2016-08-05-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The former implement, dw_mmc will push and pop the redundant data to FIFO, we should transfer it according to the real size. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | mmc: sdhci: remove the unnecessary arguments for sdhci_setup_cfgJaehoon Chung2016-08-05-25/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some arguments don't need to pass to sdhci_setup_cfg. Generic variable can be used in sdhci_setup_cfg, and some arguments are already included in sdhci_host struct. It's enough that just pass the board specific things to sdhci_setup_cfg(). After removing the unnecessary arguments, it's more simpler than before. It doesn't consider "Version" and "Capabilities" anymore in each SoC driver. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mmc: sdhci: remove the unused argument for sdhci_setup_cfgJaehoon Chung2016-08-05-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | buswidth isn't used anywhere in sdhci_setup_cfg. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported"Jaehoon Chung2016-08-05-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This "commit 429790026021d522d51617217d4b86218cca5750" is wrong. SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit. For example, Exynos didn't have CTRL_HISPD. But Highspeed mode is supported. (This quirks doesn't mean that driver didn't support the Highseepd mode.) Note: If driver didn't support the Highspeed Mode, use or add the other quirks. After applied this patch, all Exynos SoCs are just running with 25MHz. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | mmc: display mmc list information like mmc_legacy typeXu Ziyuan2016-08-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's nicer to see this: => mmc list dwmmc@ff0c0000: 0 dwmmc@ff0f0000: 1 (eMMC) than this: => mmc list dwmmc@ff0c0000: 0dwmmc@ff0f0000: 1 (eMMC) With the former, it's much clearer which mmc devices are on. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | mmc: use the generic error numberJaehoon Chung2016-08-05-90/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the generic error number instead of specific error number. If use the generic error number, it can debug more easier. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* | | mmc: fsl_esdhc: remove the duplicated header fileJaehoon Chung2016-08-05-1/+0
| | | | | | | | | | | | | | | | | | | | | "mmc.h" is already included. It's duplicated. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mmc: dw_mmc: remove the duplicated header fileJaehoon Chung2016-08-05-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | <asm-generic/errno.h> is already included in <errno.h>. It can use <errno.h> instead of <asm-generic/errno.h> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mmc: s5p_sdhci: unset the SDHCI_QUIRK_BROKEN_R1BJaehoon Chung2016-08-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unset the SDHCI_QUIRK_BROKEN_R1B for exynos SoC. (Tested on Exynos4 Boards.) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
* | | mmc: sdhci: set to INT_DATA_END when there are dataJaehoon Chung2016-08-05-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no data, it doesn't needs to wait for completing data transfer. (It seems that it can be removed.) Almost all timeout error is occured from stop command without data. After applied this patch, I hope that we don't need to increase timeout value anymore. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* | | mmc: sdhci: clean up timeout detectionMasahiro Yamada2016-08-05-9/+9
|/ / | | | | | | | | | | | | | | | | | | | | | | | | The current timeout detection logic is not very nice; it calls get_timer(start) in the while() loop, and then calls it again after the loop to check if a timeout error happened. Because of the time difference between the two calls of get_timer(), the timeout detected after the loop may not be true. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | driver/ddr/fsl: Fix timing_cfg_2York Sun2016-08-02-1/+1
| | | | | | | | | | | | | | | | | | Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
* | crypto/fsl: Update blob cmd to accept 64bit addressesSumit Garg2016-08-02-3/+10
| | | | | | | | | | | | | | | | | | Update blob cmd to accept 64bit source, key modifier and destination addresses. Also correct output result print format for fsl specific implementation of blob cmd. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | driver: spi: fsl-qspi: remove compile WarningsYunhui Cui2016-08-02-1/+3
| | | | | | | | | | | | | | | | | | | | Warnins log: drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’: drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-07-31-5/+22
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| * | rockchip: rk3288: Fix pinctrl for GPIO bank 0John Keeping2016-07-31-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | mmc-uclass: correct the device numberKever Yang2016-07-31-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | net: sun8i_emac: Fix DMA alignment issues with the rx / tx buffersHans de Goede2016-07-31-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following CACHE warnings when using sun8i_emac: => dhcp BOOTP broadcast 1 BOOTP broadcast 2 CACHE: Misaligned operation at range [7bf594a8, 7bf59628] BOOTP broadcast 3 CACHE: Misaligned operation at range [7bf59c90, 7bf59e10] CACHE: Misaligned operation at range [7bf5a478, 7bf5a5f8] DHCP client bound to address 10.42.43.80 (1009 ms) Note this commit also changes the max rx size from 2024 to 2044, matching what the kernel driver uses. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | sunxi: gpio: Add .xlate function for gpio phandle resolutionChen-Yu Tsai2016-07-31-0/+16
|/ / | | | | | | | | | | | | | | | | | | | | | | | | sunxi uses a 2 cell phandle for gpio bindings. Also there are no seperate nodes for each pin bank. Add a custom .xlate function to map gpio phandles to the correct pin bank device. This fixes gpio_request_by_name usage. Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver model") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | spi: ti_qspi: dra7xx: Add support to use 76.8MHz clockVignesh R2016-07-30-5/+12
| | | | | | | | | | | | | | | | | | | | According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update the driver to use the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | sf: sf_params: Add AT25DF321 flash supportWenyou Yang2016-07-30-1/+2
| | | | | | | | | | | | | | | | Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | spi: ti_qspi: Remove delay in read path for dra7xxVignesh R2016-07-30-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | spi: ti_qspi: Fix compiler warning when DEBUG macro is setVignesh R2016-07-30-2/+2
| | | | | | | | | | | | | | | | | | | | clk_div is uninitialized at the beginning of ti_spi_set_speed(), move debug() print after clk_div calculation to avoid compiler warning and to have proper value of clk_div printed during debugging. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | spi: ti_qspi: Fix failure on multiple READ_ID cmdVignesh R2016-07-30-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in ti_qspi_cs_deactivate(). Therefore CS is never deactivated between successive READ ID which results in sf probe to fail. Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih priv->cmd as required (similar to the convention followed in the driver). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* | spi: Add support for N25Q016AMoritz Fischer2016-07-30-0/+1
| | | | | | | | | | | | | | | | This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-8/+42
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| * | pci: allow disabling of pci init/enum via envTim Harvey2016-07-28-0/+4
| | | | | | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | serial_mxc: Remove unconditional DCE settingBreno Lima2016-07-21-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 83fd908f28c ("dm: imx: serial: Support DTE mode when using driver model") breaks the serial output for the imx boards that do not use the serial driver model. The reason for the breakage is that it's setting UFCR_DCEDTE unconditionally for the non-dm case. So keep the original behavior by removing UFCR_DCEDTE setting in the non-dm case. Tested on mx7sabresd and mx6wandboard. Signed-off-by: Breno Lima <breno.lima@nxp.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * | imx_watchdog: add weak attribute to reset_cpu functionStefan Agner2016-07-19-1/+1
| | | | | | | | | | | | | | | | | | | | | This allows to overwrite reset_cpu function in case a board level reset is preferred (e.g. through PMIC). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | usb: ehci-mx6: introduce config for high active power pinStefan Agner2016-07-19-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new config CONFIG_MXC_USB_OTG_HACTIVE which configures the OTG Power Pin to be high active. Low active is the reset value of the affected configuration register, hence the config option is named by the non-reset configuration. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | usb: ehci-mx6: configure power polarity in usb_power_configStefan Agner2016-07-19-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | USBNC_n_CTRL1 bit 9 actually controls the power pin polarity. Rename UCTRL_PM to align reference manual and set the bit in the appropriate callback usb_power_config. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | usb: move CONFIG_USB_EHCI_MX7 to KconfigStefan Agner2016-07-19-0/+7
| | | | | | | | | | | | | | | | | | | | | Create an entry for "config USB_EHCI_MX7" in Kconfig and switch over to it for all boards. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | dm: imx: serial: Support DTE mode when using driver modelStefan Agner2016-07-19-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MXC UART IP can be run in DTE or DCE mode. This depends on the board wiring and the pinmux used and hence is board specific. This extends platform data with a new field to choose wheather DTE mode shall be used. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | driver/net/fec: support fixed speed connectionHannes Schmelzer2016-07-12-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | If MAC is directly connected to another MAC (like a switch for example) we don't need to probe for a phy, autoneogation and so on. We simply have to setup speed. Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | pcie_imx: increment timeout for link upStefano Babic2016-07-12-1/+1
| |/ | | | | | | | | | | | | On some boards, the current 20ms timeout is hit. Increase it to 40mS. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-07-27-199/+451
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| * | mmc: dw_mmc: reduce timeout detection cycleXu Ziyuan2016-07-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's no need to speed 10 seconds to wait the mmc device out from busy status. 500 milliseconds enough. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
generated by cgit v1.1 at 2024-11-07 21:30:03 +0000