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authorChin Liang See <clsee@altera.com>2016-08-07 22:50:40 +0800
committerMarek Vasut <marex@denx.de>2016-08-07 21:54:21 +0200
commit5405817a6e7a6538c4bcb1c3076ddc83fe5d03f9 (patch)
tree2a5b2c7cdf863fc4c7b18745c0fa16c26b05b38a /drivers
parent2da375c9194ad85fc117088a8ebbca192b685207 (diff)
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spi: cadence_qspi_apb: Ensure baudrate doesn't exceed max value
Ensuring the baudrate divisor value doesn't exceed the max value in the calculation.It will be capped at max value to ensure the correct value being written into the register. Example of the existing bug is when calculated div = 16. After and with the mask, the value written to register is actually 0 (register field for baudrate divisor). With this fix, the value written is now 15 which is max value for baudrate divisor. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jteki@openedev.com> Cc: Dinh Nguyen <dinguyen@altera.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/cadence_qspi_apb.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 1a35d55..1d68379 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -293,8 +293,11 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base,
debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
ref_clk_hz, sclk_hz, div);
- div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
- reg |= div;
+ /* ensure the baud rate doesn't exceed the max value */
+ if (div > CQSPI_REG_CONFIG_BAUD_MASK)
+ div = CQSPI_REG_CONFIG_BAUD_MASK;
+
+ reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base);