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* pci: mvebu: Add PCIe driverAnton Schubert2015-08-17-0/+424
| | | | | | | | | | | | | | | | | | | This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the driver, this patch also removes the statically defined PCI MBUS windows. As they are not needed anymore, since this PCIe driver now creates the windows dynamically. Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000 PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp eval board using this Intel E1000 PCIe card in the PCIe 0 slot. This port was done in cooperation with Anton Schubert. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
* arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-17-2/+2
| | | | | | | | | | | | This patch introduces the SDRAM scrubbing for ECC enabled board to fill/initialize the ECC bytes. This is done via the XOR engine to speed up the process. The scrubbing is a 2-stage process: 1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot 2) U-Boot scrubs the remaining SDRAM area(s) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: add multiple usb-hostcontroller support for AXPAnton Schubert2015-08-17-8/+11
| | | | | | | | | | | This patch adds support for multiple hostcontrollers to the ehci-marvell driver and enables all 3 usb-hcs on the db-mv784mp-gp board. It depends on the initial Armada XP usb support patch from Stefan. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Enable USB EHCI support on Armada XPStefan Roese2015-08-17-1/+8
| | | | | | | | | | | | | | | | | This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU. Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Enable NAND controller on MVEBU SoC'sStefan Roese2015-08-17-1/+0
| | | | | | | | | | | | | This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on the DB-MV784MP-GP eval board. To really enable ECC support on this board the I2C EEPROM needs to get changed. As it saves the enabling of ECC support internally. For this the following commands can be used to enable ECC support on this board: Its recommended for first save (print) the value(s) in this EEPROM address: => i2c md 4e 0.1 2 0000: 05 00 .. To enable ECC support you need to set bit 1 in the 2nd byte: Marvell>> i2c mw 4e 1.1 02 Marvell>> i2c md 4e 0.1 2 0000: 05 02 .. To disable ECC support again, please use this command: Marvell>> i2c mw 4e 1.1 00 Marvell>> i2c md 4e 0.1 2 0000: 05 00 .. On other AXP boards, simply plugging an ECC DIMM should be enough to enable ECC support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* i2c: lpc32xx: fix write timeoutSylvain Lemieux2015-08-17-0/+2
| | | | | | Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when parameters alen = 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* i2c: lpc32xx: fix read timeoutSylvain Lemieux2015-08-17-5/+5
| | | | | | Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when parameters alen != 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* i2c: lpc32xx: use api to get hclk instead of fix valueSylvain Lemieux2015-08-17-1/+1
| | | | | | The HCLK is not constant and can take different value; use the api function to get the value of the HCLK for the I2C clock high and low computation. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-14-1/+141
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| * video: vesa: Correct a typo in the Kconfig VESA mode stringBin Meng2015-08-14-1/+1
| | | | | | | | | | | | | | There is one typo in the VESA mode 105h string. Correct it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Revert "dm: pci: Allow scan bridge child devices before relocation"Simon Glass2015-08-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit df189d9ba3f8fd1bc67e3c0c3c4ace16cd065ee1. Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices before relocation and there is not enough pre-reloc malloc() memory. Rathar then increase this memory, revert for now until we figure this out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Add a way to iterate through all PCI devicesSimon Glass2015-08-14-0/+60
| | | | | | | | | | | | | | | | | | These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Provide friendly config access functionsSimon Glass2015-08-14-0/+76
| | | | | | | | | | | | | | | | | | At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-pmicTom Rini2015-08-14-1/+104
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| * | Add missing part of: "power: pmic: pfuze100 support driver model"Peng Fan2015-08-14-1/+104
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This part of mentioned commit, was missed by my mistake during the rebase. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Original commit message: power: pmic: pfuze100 support driver model 1. Support driver model for pfuze100. 2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100 3. This driver intends to support PF100, PF200 and PF3000, so add the device id into the udevice_id array. 4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS. Change-Id: I4fc88414f3c0285f9648e47ec7aed60addeccc4d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sunxi: Display: Add support for eDP panels connected via an anx9804 bridgeHans de Goede2015-08-14-1/+18
| | | | | | | | | | | | | | | | | | | | | | Add support for 4 1.62G lane eDP panels connected via an anx9804 bridge, such as found on the Colombus devkit. While at it also fix the wrong indentation of the SSD2828 Kconfig help text in board/sunxi/Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | video: Add support for the ANX9804 parallel lcd to dp bridge chipHans de Goede2015-08-14-0/+222
| | | | | | | | | | | | | | | | | | Add support for the ANX9804 bridge chip, which can take pixel data coming from a parallel LCD interface and translate it on the fly into a DP interface for driving eDP TFT displays. It uses I2C for configuration. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* | sun6i: display: Add support for using the mipi pll as lcd clock sourceHans de Goede2015-08-14-7/+34
| | | | | | | | | | | | | | | | | | Add support for using the mipi pll as lcd clock source, this is necessary for getting higher dotclocks with lcd panels. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* | sunxi: gpio: Add support for the gpio banks which are part of the R-io clusterHans de Goede2015-08-14-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | sun6i and later have a couple of io-blocks which are shared between the main CPU core and the "R" cpu which is small embedded cpu which can be active while the main system is suspended. These gpio banks sit at a different mmio address then the normal banks, and have a separate devicetree node and compatible, this adds support for these banks to the sunxi-gpio code when built with device-model support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: display: Fix composite video out on sun5iHans de Goede2015-08-14-0/+11
| | | | | | | | | | | | | | | | The tv-encoder on sun5i is slightly different compared to the one on sun4i/sun7i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: display: Add overscan correctionHans de Goede2015-08-14-12/+39
| | | | | | | | | | | | | | | | | | | | | | Add support for making the visual area of the framebuffer smaller and drawing a black border around it. This is intended for use with overscanning monitors (esp. with composite video out), to avoid part of the picture being invisible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* | cfbconsole: Add support for stride != widthHans de Goede2015-08-14-35/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | cfbconsole currently assumes that the width and stride of the framebuffer are the same, in most places where stride matters it uses a VIDEO_LINE_LEN helper macro. This commit changes the few places not using VIDEO_LINE_LEN to also use VIDEO_LINE_LEN, and protects the default VIDEO_LINE_LEN with a #ifndef guard, allowing the boards config.h to override and, and thus support cases where stride != width. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* | cfbconsole: Remove width argument from the logo functionsHans de Goede2015-08-14-13/+8
|/ | | | | | | | The passed in width is always VIDEO_COLS. This is a preparation patch for adding stride != width support to the cfbconsole code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* tegra: nand: disable subpage writesMarcel Ziswiler2015-08-13-0/+3
| | | | | | | | Disable subpage writes as we do not provide ecc->hwctl. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mtd/nand/tegra: alignment workaroundMarcel Ziswiler2015-08-13-51/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Integrate cache alignment bounce buffer to workaround issues as follows: Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)... ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Done Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ] Starting kernel ... undefined instruction pc : [<005ff03c>] lr : [<0000800c>] sp : 0144b6e8 ip : 01000188 fp : 0144a6c8 r10: 00000000 r9 : 411fc090 r8 : 00000100 r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000 r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: fix read_byte required for proper onfi detectionMarcel Ziswiler2015-08-13-31/+7
| | | | | | | | | | | | | | | | | | Fix PIO read_byte() implementation not only used for the legacy READ ID but also the PARAM command required for proper ONFI detection. This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late (not mainline yet but getting there soon I hope). I vaguely remember that those commands are special on 16-bit bus NAND (e.g. always return 8-bit data regardless) and later Linux MTD fixed/ changed the way this is handled which in turn broke once U-Boot pulled that in. Basically instead of doing PIO read regular DMA block read is now used which this patch actually fixes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2015-08-13-22/+47
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| * mmc_spi: Big-endian supportYoshinori Sato2015-08-13-5/+5
| | | | | | | | | | | | | | Currently implement always swap for big-endian value. So doesn't work big-endian environment. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
| * dw_mmc: Calculate dwmmc FIFO threshold size if not providedSimon Glass2015-08-13-2/+8
| | | | | | | | | | | | | | | | | | We can calculate this. Add code to do this if it is not provided. panto: prefix changed to dw_mmc to make things easier to grep Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: dw_mmc: Avoid using printf() for errorsSimon Glass2015-08-11-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | The dw_mmc driver uses printf() in various places. These bloat the code and cause problems for SPL. Use debug() where possible and try to return a useful error code instead. panto: Small rework to make it apply against top of tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: dw_mmc: Improve handling of data transfer failureMarek Vasut2015-08-11-7/+9
| | | | | | | | | | | | | | | | | | | | | | In case the data transfer failure happens, instead of returning immediatelly, make sure the DMA is disabled, status register is cleared and the bounce buffer is stopped. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
| * mmc: dw_mmc: Zap endless timeoutMarek Vasut2015-08-11-2/+17
| | | | | | | | | | | | | | | | | | | | Endless timeouts are bad, since if we get stuck in one, we have no way out. Zap this one by implementing proper timeout. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
| * mmc: dw_mmc: Stop bounce buffer even in case of failureMarek Vasut2015-08-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The driver didn't stop the bounce buffer in case a data transfer failed. This would lead to memory leakage if the communication between the CPU and the card is unreliable. Add the missing call to stop the bounce buffer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* | net: lpc32xx: eth buffers base configSylvain Lemieux2015-08-13-3/+5
| | | | | | | | | | | | | | | | Add support to specify the Ethernet buffer base address; if none are supply by the board, the default value is use (from existing code). Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-08-13-54/+202
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| * | net: e1000: Increase autoneg timeout to 8 secondsStefan Roese2015-08-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current 4.5 timeout for the autonegotiation are not enough to complete it on my platform. Using the Intel E1000 PCIe card in the Marvell db-mv784mp-gp eval board. So lets increase the timeout to 8 seconds. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org>
| * | net: phy: broadcom: Add BCM Cygnus PHYJiandong Zheng2015-08-11-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | Add Ethernet PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: delay only if reset handler is registeredJörg Krause2015-08-11-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only reset if a reset handler is registered. If there is no reset handler there is no need to wait for a device to come out of the reset. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
| * | net: phy: fix data type of phy_idJörg Krause2015-08-11-1/+1
| | | | | | | | | | | | | | | | | | phy_id is declared as u32 in create_phy_by_mask and in struct phy_device. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
| * | qoriq eth.c bugfix: handle received corrupted frames correctlyDaniel Inderbitzin2015-08-11-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The rxbd is not correctly handled in case of a frame physical error (FPE) or frame size error (FSE). The rxbd must be cleared and advanced in case of an error to avoid receive stall. Signed-off-by: Daniel Inderbitzin <daniel.inderbitzin@gmail.com>
| * | net: lpc32xx: add RMII phy mode supportVladimir Zapolskiy2015-08-11-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LPC32xx MAC and clock control configuration requires some minor quirks to deal with a phy connected by RMII. It's worth to mention that the kernel and legacy BSP from NXP sets SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011 and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also in my tests an SMSC LAN8700 phy device connected over RMII seems to work correctly without touching this bit. Add support of RMII, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already define the same config value. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
| * | net: lpc32xx: improve MAC configuration on reset and initializationVladimir Zapolskiy2015-08-11-18/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change rearranges general MAC configuration and PHY specific configuration of MAC registers (duplex mode and speed), before this change set bits related to PHY configuration in MAC2 and COMMAND registers are rewritten by the following writing to the registers. Without the change auto negotiation on boot quite often is not completed in reasonable time: Waiting for PHY auto negotiation to complete......... TIMEOUT ! Additionally MAC1_SOFT_RESET clear bit is removed since it is done in preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead added missing MCFG_RESET_MII_MGMT on device initialization. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
| * | net: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR idVladimir Zapolskiy2015-08-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX MAC to some specified phy by phy id, by chance the single user of lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may have non-zero CONFIG_PHY_ADDR value, fix it. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: lpc32xx: correct command register reset valueVladimir Zapolskiy2015-08-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to LPC32x0 User Manual the following bits in Command register 0x3106_0100 are defined: Bit Symbol 2 - Unused 3 RegReset 4 TxReset 5 RxReset Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets an unused bit, but neglects RxReset. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: davinci_emac: don't teardown inactive rx channelJeroen Hofstee2015-08-11-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tearing down an unitialized rx channel causes a pending address hole event to be queued. When booting linux it will report this pending as something like "Address Hole seen by USB_OTG at address 57fff584", since u-boot did not handled this interrupt. Prevent that by not tearing down the rx channel, when not receiving. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * | net: Add support for Marvell 88E1510 PHYClemens Gruber2015-08-11-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support the 88E1510 PHY which is very similar to the 88E1518. I also set the INTn output and configured the LEDs. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: Improve 88E151x PHY initializationClemens Gruber2015-08-11-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: macb: add gmac multi-queue supportWu, Josh2015-08-11-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch refer to linux kernel commit: d8b763e1e79f net/macb: add TX multiqueue support for gem by: Cyrille Pitchen 1. macb driver will check the register to find how many queues support for this chip. 2. Then as we only use queue0 for tx, so we will set up all other queues use a dummy descriptor, which USED bit is set. So those queues are not used. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net/phy: set led for rtl8211f phyShengzhou Liu2015-08-11-0/+8
| | | | | | | | | | | | | | | | | | | | | Initialize LCR rigister to configure green LED for Link, yellow LED for Active. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
generated by cgit v1.1 at 2024-11-05 10:35:07 +0000