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* mmc:fsl_esdhc invalidate dcache before readPeng Fan2015-07-26-0/+8
| | | | | | | | | | | | | | | | | | | | | DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* power: pmic: Add support for MAX77696 PMICFabio Estevam2015-07-26-0/+33
| | | | | | Add support for MAX77696 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-1044/+445
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| * Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-15-963/+314
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| | * pci: Disable expansion ROM address decoding when signature check failsBin Meng2015-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter <mporter@konsulko.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * pci: Configure expansion ROM during auto config processBin Meng2015-07-14-31/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| | * drivers: block: Remove the ata_piix driverBin Meng2015-07-14-789/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * x86: pci: Tidy up the generic x86 PCI driverSimon Glass2015-07-14-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: spi: Correct BIOS protection logic for ICH9Simon Glass2015-07-14-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
| | * dm: spi: Correct status register access widthSimon Glass2015-07-14-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| | * x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-14-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
| | * x86: Move VGA option rom macros to KconfigBin Meng2015-07-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * video: Add 32-bit color depth support for VBEJian Luo2015-07-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| | * video: vesa_fb: Look up VGA device by class instead of idBin Meng2015-07-14-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-14-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * dm: rtc: Support mc146818 driver in driver modelBin Meng2015-07-14-108/+204
| | | | | | | | | | | | | | | | | | | | | | | | Add driver model support to the mc146818 rtc driver. Also clean up the driver a little bit for coding convention issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * x86: Move MP initialization codes into a common placeBin Meng2015-07-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the new 'get_count' method for baytrail and cpu_x86 drivers. Now we call cpu_get_count() in mp_init() to get the number of CPUs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: cpu: Add a new get_count method to cpu uclassBin Meng2015-07-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: cpu: Test against cpu_ops->get_info in cpu_get_info()Bin Meng2015-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| | * dm: cpu: Fix undefined ENOSYS build errorBin Meng2015-07-14-0/+1
| | | | | | | | | | | | | | | | | | | | | Include <errno.h> otherwise ENOSYS is undefined. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * dm: spi: Correct minor nits in ICH driverSimon Glass2015-07-14-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Tidy up three minor problems in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-07-14-36/+28
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| | * spi: cadence_qspi: support FIFO width other than 4 bytesVikas Manocha2015-07-03-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the code compatible with FIFO depths other than 4 bytes. It also simplify read/write FIFO loops. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * spi: cadence_qspi: get sram size from device treeVikas Manocha2015-07-03-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | sram size could be different on different socs, e.g. on stv0991 it is 256 while on altera platform it is 128. It is better to receive it from device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| | * spi: cadence_qspi: move the sram partition in initVikas Manocha2015-07-03-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
| * | Merge git://git.denx.de/u-boot-samsungTom Rini2015-07-10-1/+1
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| | * | exynos: i2c: Correct bug in pinmux selectionSimon Glass2015-07-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When driver model is not used the current code does not correctly select the pinmux for the I2C bus. This bug was introduced by this commit: 8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Merge git://git.denx.de/u-boot-marvellTom Rini2015-07-10-8/+56
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| | * | | usb: Add EHCI support for Armada 38x (mvebu)Stefan Roese2015-07-10-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| | * | | block: ahci: Don't enable port interruptsStefan Roese2015-07-10-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the initialization of the AHCI controller to not enable the default interrupts (DEF_PORT_IRQ). As interrupts are not used in U-Boot in general, this should not break the common AHCI driver operation. This change is needed to support the Marvell Armada 38x AHCI controller. With interrupts enabled, this results in timeouts in ahci_device_data_io(). Not enabling these interrupts fixes this problem and the common AHCI driver works fine. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| | * | | mmc: sdhci.c: Add config option to use a fixed buffer for transfersStefan Roese2015-07-10-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the following problem occured. The SPL runs in internal SRAM which is the L2 cache locked to memory. When the MMC buffers now are located on the stack (or bss), the SDIO controller (SDHCI) can't write into this L2 cache memory. This patch introduces a method to use a fixed buffer that will be used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER. This way, the board can use this buffer address located in SDRAM for all transfers. This solves this SPL problem on the A38x and should only be used in the SPL U-Boot version. Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| | * | | mmc: sdhci: Use timer based timeout detection in sdhci_send_command()Stefan Roese2015-07-10-5/+5
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The loop counter based timeout detection does not work on the Armada 38x based board (DB-88F6820-GP). At least with dcache enabled a timeout is detected. Without dcache enabled, the timeout does not occur. Increasing the loop counter solves this issue. But a better solution is to use a timer based timeout detection instead. This patch now implements this timer based detection. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | | mtd: fix false positive "Offset exceeds device limit" errorMasahiro Yamada2015-07-10-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | ahci: Fix compiling warnings under 64bit platformsTang Yuantian2015-07-09-34/+43
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; ^ drivers/block/ahci.c: In function ?.hci_host_init?. drivers/block/ahci.c:218:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); ...... Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* | | thermal: imx_thermal: fix busywait if IMX6 temp <0CTim Harvey2015-07-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The temperature calculation must be typecasted to keep the compiler from sign extending a negative value prior to division. This fixes an issue where if the CPU temperature is <0C it will get stuck in the busywait loop until the CPU heats up to 0C. Cc: Ye Li <b37916@freescale.com> Cc: Jason Liu <r64343@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | | i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-10-1/+2
| | | | | | | | | | | | | | | | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* | | net: fec_mxc: remove useless struct nbufAlbert ARIBAUD \(3ADEV\)2015-07-10-15/+5
| | | | | | | | | | | | | | | | | | | | | | | | This locally defined struct is actually only used once and as an opaque type. Remove it for clarity. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | thermal:imx_thermal: enter busywait cooling loop when over max CPU tempTim Harvey2015-07-10-10/+6
|/ / | | | | | | | | | | | | | | | | | | | | | | Remove the check for temperature being within the min/max range and enter the busywait cooling loop whenever the CPU temperature is over the critical temp. This fixes the issue where if a board was booted at a temp greater than the CPU temperature max, it would skip the loop and never indicate or try to address the overtemp issue. Cc: Ye Li <b37916@freescale.com> Cc: Jason Liu <r64343@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | net: designware: Program MAC address to hardware after soft resetBin Meng2015-07-08-0/+6
| | | | | | | | | | | | | | | | | | | | commit f566c99 "net: Update hardware MAC address if it changes in env" removes writing MAC address to designware controller after soft reset. This makes designware ethernet port fail to work. Actually the MAC address should always be programmed after soft reset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-07-07-20/+35
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| * arm: dcc: Add uart dcc support for armv8Siva Durga Prasad Paladugu2015-07-07-0/+16
| | | | | | | | | | | | | | | | Added UART DCC support for armv8 Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-07-797/+2019
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| * | gpio: lpc32xx: Use priv_data instead of platdataAxel Lin2015-07-07-20/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | The LPC32XX GPIO driver platdata currently contains GPIO state information, which should go into priv_data. Thus rename lpc32xx_gpio_platdata to lpc32xx_gpio_priv and convert to use dev_get_priv() instead. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
* | | spi: cf_qspi: fix clamp macro type check compilation warningsAngelo Dureghello2015-07-01-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix compilation warnings for redefined 'clamp' macro and non-uniform clamp macro types. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | | sf: Kconfig: Add SPI_FLASH_BAR entryJagan Teki2015-07-01-0/+8
| | | | | | | | | | | | | | | | | | Added SPI_FLASH_BAR entry on Kconfig with help description Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | spi: Kconfig: Add TEGRA20_SLINK entryJagan Teki2015-07-01-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added TEGRA20_SLINK entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* | | spi: Kconfig: Add TEGRA20_SFLASH entryJagan Teki2015-07-01-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added TEGRA20_SFLASH entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* | | spi: Kconfig: Add TEGRA114_SPI entryJagan Teki2015-07-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added TEGRA114_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.1 at 2024-12-28 06:46:51 +0000